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[8.43.85.97]) by mx.google.com with ESMTPS id w1-20020aa7dcc1000000b005230f1ff03esi272713edu.275.2023.08.02.20.30.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 20:30:05 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=g+EQQsg7; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9BFBC3858C20 for ; Thu, 3 Aug 2023 03:30:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9BFBC3858C20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1691033404; bh=bbls4LWaPvhMKwfJmrpdPh9BCzF16GeWrrwMfVjRf80=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=g+EQQsg7pWjmy+/BvSOZnhqC47DXn4mi759FbtU9rkZrnHkoL/4GovVN/6LjPQeHa P8mmfy0A40e+EesugZ1xuaEk7DLYLzifcBRLNvc1HUoIqYkx5S8+xP+mgWN2+1JKHn zNISep5pNSVnJq2I+l/o3o+TgXwmLz55KRJ08dZE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 50D7F3858D1E for ; Thu, 3 Aug 2023 03:29:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 50D7F3858D1E X-IronPort-AV: E=McAfee;i="6600,9927,10790"; a="349355175" X-IronPort-AV: E=Sophos;i="6.01,251,1684825200"; d="scan'208";a="349355175" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2023 20:29:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10790"; a="732586340" X-IronPort-AV: E=Sophos;i="6.01,251,1684825200"; d="scan'208";a="732586340" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga007.fm.intel.com with ESMTP; 02 Aug 2023 20:29:17 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 78AC310083B2; Thu, 3 Aug 2023 11:29:16 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support RVV VFDIV and VFRDIV rounding mode intrinsic API Date: Thu, 3 Aug 2023 11:29:14 +0800 Message-Id: <20230803032914.819141-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773177044420292338 X-GMAIL-MSGID: 1773177044420292338 From: Pan Li This patch would like to support the rounding mode API for the VFDIV and VFRDIV for the below samples. * __riscv_vfdiv_vv_f32m1_rm * __riscv_vfdiv_vv_f32m1_rm_m * __riscv_vfdiv_vf_f32m1_rm * __riscv_vfdiv_vf_f32m1_rm_m * __riscv_vfrdiv_vf_f32m1_rm * __riscv_vfrdiv_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (binop_frm): New declaration. (reverse_binop_frm): Likewise. (BASE): Likewise. * config/riscv/riscv-vector-builtins-bases.h: (vfdiv_frm): New extern declaration. (vfrdiv_frm): Likewise. * config/riscv/riscv-vector-builtins-functions.def (vfdiv_frm): New function definition. (vfrdiv_frm): Likewise. * config/riscv/vector.md: Add vfdiv to frm_mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-div.c: New test. * gcc.target/riscv/rvv/base/float-point-single-rdiv.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li > --- .../riscv/riscv-vector-builtins-bases.cc | 6 +++ .../riscv/riscv-vector-builtins-bases.h | 2 + .../riscv/riscv-vector-builtins-functions.def | 3 ++ gcc/config/riscv/vector.md | 2 +- .../riscv/rvv/base/float-point-single-div.c | 44 +++++++++++++++++++ .../riscv/rvv/base/float-point-single-rdiv.c | 33 ++++++++++++++ 6 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 3adc11138a3..95ec9ccb481 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -278,6 +278,7 @@ public: /* Implements below instructions for now. - vfadd - vfmul + - vfdiv */ template class binop_frm : public function_base @@ -301,6 +302,7 @@ public: /* Implements below instructions for frm - vfrsub + - vfrdiv */ template class reverse_binop_frm : public function_base @@ -2106,7 +2108,9 @@ static CONSTEXPR const widen_binop_frm vfwsub_frm_obj; static CONSTEXPR const binop vfmul_obj; static CONSTEXPR const binop_frm vfmul_frm_obj; static CONSTEXPR const binop
vfdiv_obj; +static CONSTEXPR const binop_frm
vfdiv_frm_obj; static CONSTEXPR const reverse_binop
vfrdiv_obj; +static CONSTEXPR const reverse_binop_frm
vfrdiv_frm_obj; static CONSTEXPR const widen_binop vfwmul_obj; static CONSTEXPR const vfmacc vfmacc_obj; static CONSTEXPR const vfnmsac vfnmsac_obj; @@ -2338,7 +2342,9 @@ BASE (vfwsub_frm) BASE (vfmul) BASE (vfmul_frm) BASE (vfdiv) +BASE (vfdiv_frm) BASE (vfrdiv) +BASE (vfrdiv_frm) BASE (vfwmul) BASE (vfmacc) BASE (vfnmsac) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 9c12a6b4e8f..f35fd3d27cf 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -154,7 +154,9 @@ extern const function_base *const vfwsub_frm; extern const function_base *const vfmul; extern const function_base *const vfmul_frm; extern const function_base *const vfdiv; +extern const function_base *const vfdiv_frm; extern const function_base *const vfrdiv; +extern const function_base *const vfrdiv_frm; extern const function_base *const vfwmul; extern const function_base *const vfmacc; extern const function_base *const vfnmsac; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 35a83ef239c..e7e6c7d8ed8 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -321,6 +321,9 @@ DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfrdiv, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvv_ops) DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvf_ops) +DEF_RVV_FUNCTION (vfdiv_frm, alu_frm, full_preds, f_vvv_ops) +DEF_RVV_FUNCTION (vfdiv_frm, alu_frm, full_preds, f_vvf_ops) +DEF_RVV_FUNCTION (vfrdiv_frm, alu_frm, full_preds, f_vvf_ops) // 13.5. Vector Widening Floating-Point Multiply DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 5d3e4256cd5..4b6c3859947 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -866,7 +866,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" - (cond [(eq_attr "type" "vfalu,vfwalu,vfmul") + (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv") (cond [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") (const_string "rne") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c new file mode 100644 index 00000000000..cef6ab007b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfdiv_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfdiv_vv_f32m1_rm (op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfdiv_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfdiv_vv_f32m1_rm_m (mask, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfdiv_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfdiv_vf_f32m1_rm (op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfdiv_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfdiv_vf_f32m1_rm_m (mask, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfdiv_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfdiv_vv_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfdiv_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfdiv_vv_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfdiv\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c new file mode 100644 index 00000000000..385cddf5070 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_vfrdiv_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfrdiv_vf_f32m1_rm (op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfrdiv_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfrdiv_vf_f32m1_rm_m (mask, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfrdiv_vf_f32m1 (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfrdiv_vf_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfrdiv_vf_f32m1_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfrdiv_vf_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfrdiv\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */