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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id gg25-20020a170906e29900b0099381745ba7si10160460ejb.878.2023.08.02.01.01.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 01:01:07 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=b1RK8wRe; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C8FE5385841E for ; Wed, 2 Aug 2023 08:01:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C8FE5385841E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690963265; bh=Zw/BexjUEVIcOJDmQJedDFmnT1pwOg5xnZPWdu+RiO0=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=b1RK8wReV7FMTWyuVoGXYH5GSTG3VKC0HHeS7Ety62S9Cjy8s57M5Pyc/D+qqP6RK jQsq14gNK5kP2ds52qbLL27KWmvAGHh66LebeZEnKgofoMaERNiqw8Wjetg5JdfbDe NDB0KsKODVJXdaxXUIZt1zD1Yuo3q8Qac0yPyHBc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (unknown [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 33BF93858CDA for ; Wed, 2 Aug 2023 07:59:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 33BF93858CDA X-IronPort-AV: E=McAfee;i="6600,9927,10789"; a="359555283" X-IronPort-AV: E=Sophos;i="6.01,248,1684825200"; d="scan'208";a="359555283" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2023 00:59:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10789"; a="678974107" X-IronPort-AV: E=Sophos;i="6.01,248,1684825200"; d="scan'208";a="678974107" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga003.jf.intel.com with ESMTP; 02 Aug 2023 00:59:26 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 753CF1007EA9; Wed, 2 Aug 2023 15:59:25 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding Date: Wed, 2 Aug 2023 15:59:24 +0800 Message-Id: <20230802075924.3448107-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773103498990629532 X-GMAIL-MSGID: 1773103498990629532 From: Pan Li This patch would like to enhance the vfsub/vfrsub rounding API test for below 2 purposes. * The non-rm API has no frm related insn generated. * The rm API has the frm backup/restore/set insn generated. Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-rsub.c: Enhance cases. * gcc.target/riscv/rvv/base/float-point-single-sub.c: Ditto. Signed-off-by: Pan Li --- .../riscv/rvv/base/float-point-single-rsub.c | 16 +++++++++++++++- .../riscv/rvv/base/float-point-single-sub.c | 16 +++++++++++++++- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c index 1d770adc32c..86c56b7c6cb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c @@ -16,4 +16,18 @@ test_vfrsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, return __riscv_vfrsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl); } -/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +vfloat32m1_t +test_vfrsub_vf_f32m1 (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfrsub_vf_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfrsub_vf_f32m1_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfrsub_vf_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c index 34ed03a31d9..8075dced0b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c @@ -27,4 +27,18 @@ test_vfsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, return __riscv_vfsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl); } -/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ +vfloat32m1_t +test_riscv_vfsub_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfsub_vv_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfsub_vv_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */