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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id o11-20020aa7d3cb000000b0051a4adabcb5si8683353edr.618.2023.07.25.11.06.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 11:06:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=chv3jVqF; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1C0333895FEA for ; Tue, 25 Jul 2023 18:03:43 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id AA169385480C for ; Tue, 25 Jul 2023 18:02:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AA169385480C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1b8ad9eede0so46311365ad.1 for ; Tue, 25 Jul 2023 11:02:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690308151; x=1690912951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Mgf84eOaWBFUn5F7aR4Zzc51SlMwuowCK1mCDpwlrY=; b=chv3jVqFgRBlqnlJnaFx4/tyQrfobfgZN583uroDnHkVqI+m38I+pIbesvOFSh7viR PvrsK68Gc7b5Dyiufje6h5SiVZm8LnuVS3dFwE/uOhSZryqDTlW77Ae0VF4Ria5n1tQp dscxezMAau3rQkDhWnaYO5NUdrV6NZCKbxmz7XpvSbWCwFcBZUfvMrRtK6CdQg9IrnKG pOj52PAjtlM2/QJBEs2Bn9QSad+xBA2uOhbGl0t9+VBJiFkX8WRZcAxE3RDCBA6ZVCnd zwVW+5BkIBuKV17HEL3GWlkECpNQs0hBlL4Jyj4cYJUH2MC7CrBN4fZmMIaSl7BVZ66E ge0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690308151; x=1690912951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Mgf84eOaWBFUn5F7aR4Zzc51SlMwuowCK1mCDpwlrY=; b=HsnqGlOSRiYbKHkuQA6hZ9VqiPsQ26ENf55y8BzCyNWTYgNUeD1tblAr5yWNMfo+qH pqOPvp5ldjjnistoMsaKf+IDPJVVYfpGDSHKdL0OPz3Vx8P6o0OtOBjoh9F32iFEaFeU Xgynh/PYlvGaNlps4xpCinbkNknyu5WC7OQv7w75BIQ29WAWtkPhEuQ3T5/cWOeTkUKr yuHtsNokFVSuRIAlhhtedHHmvgnOV9Pe+WgIz06w4NcAqiTDwAYmSD+SQhy7f4px1q9f 8fDPOPdLqFIuIlPGWscKo4V7jce7l9OH1hZ+uTn9ZUp7UAlZWHGwoQDykd+i7mtHlnwC FdAg== X-Gm-Message-State: ABy/qLaKXmQiclZK7+hEk51AmRaRGsY4WWfKxjGhLqpNpjrL8n4G7Rfl Gm6IGZmAQ6z60hRWNG3AY2otaPedQmynkK6mp5o= X-Received: by 2002:a17:902:e542:b0:1bb:8c42:79ef with SMTP id n2-20020a170902e54200b001bb8c4279efmr14866plf.46.1690308151288; Tue, 25 Jul 2023 11:02:31 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id p1-20020a1709028a8100b001b3ce619e2esm11283352plo.179.2023.07.25.11.02.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 11:02:30 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, palmer@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [gcc13 backport 06/12] RISC-V: Strengthen atomic stores Date: Tue, 25 Jul 2023 11:02:00 -0700 Message-Id: <20230725180206.284777-7-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230725180206.284777-1-patrick@rivosinc.com> References: <20230427162301.1151333-1-patrick@rivosinc.com> <20230725180206.284777-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1764347392008617221 X-GMAIL-MSGID: 1772416837581937981 This change makes atomic stores strictly stronger than table A.6 of the ISA manual. This mapping makes the overall patchset compatible with table A.7 as well. 2023-04-27 Patrick O'Neill PR target/89835 gcc/ChangeLog: * config/riscv/sync.md (atomic_store): Use simple store instruction in combination with fence(s). gcc/testsuite/ChangeLog: * gcc.target/riscv/pr89835.c: New test. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 21 ++++++++++++++++++--- gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++ 2 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 5620d6ffa58..1acb78a9ae4 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -56,7 +56,9 @@ ;; Atomic memory operations. -;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. +;; Implement atomic stores with conservative fences. Fall back to fences for +;; atomic loads. +;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") (unspec_volatile:GPR @@ -64,9 +66,22 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,w\;" + "s\t%z1,%0\;" + "fence\trw,rw"; + if (model == MEMMODEL_RELEASE) + return "fence\trw,w\;" + "s\t%z1,%0"; + else + return "s\t%z1,%0"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 12))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c new file mode 100644 index 00000000000..ab190e11b60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr89835.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that relaxed atomic stores use simple store instuctions. */ +/* { dg-final { scan-assembler-not "amoswap" } } */ + +void +foo(int bar, int baz) +{ + __atomic_store_n(&bar, baz, __ATOMIC_RELAXED); +}