diff mbox series

[gcc13,backport,05/12] RISC-V: Add AMO release bits

Message ID 20230725180206.284777-6-patrick@rivosinc.com
State Unresolved
Headers
Series RISC-V: Implement ISA Manual Table A.6 Mappings |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Patrick O'Neill July 25, 2023, 6:01 p.m. UTC 
  This patch sets the relevant .rl bits on amo operations.

2023-04-27 Patrick O'Neill <patrick@rivosinc.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_print_operand): Change behavior
	of %A to include release bits.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/config/riscv/riscv.cc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 11b897aca5c..df55c427b1b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4498,8 +4498,13 @@  riscv_print_operand (FILE *file, rtx op, int letter)
       break;
 
     case 'A':
-      if (riscv_memmodel_needs_amo_acquire (model))
+      if (riscv_memmodel_needs_amo_acquire (model)
+	  && riscv_memmodel_needs_release_fence (model))
+	fputs (".aqrl", file);
+      else if (riscv_memmodel_needs_amo_acquire (model))
 	fputs (".aq", file);
+      else if (riscv_memmodel_needs_release_fence (model))
+	fputs (".rl", file);
       break;
 
     case 'F':