diff mbox series

[v2] RISC-V: Fixbug for fsflags instruction error using immediate.

Message ID 20230725072816.1629-1-jinma@linux.alibaba.com
State Unresolved
Headers
Series [v2] RISC-V: Fixbug for fsflags instruction error using immediate. |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Jin Ma July 25, 2023, 7:28 a.m. UTC 
  The pattern mistakenly believes that fsflags can use immediate numbers,
but in fact it does not support it. Immediate numbers should use fsflagsi.

For example:
__builtin_riscv_fsflags(4);

The following error occurred.
/tmp/ccoWdWqT.s: Assembler messages:
/tmp/ccoWdWqT.s:14: Error: illegal operands `fsflags 4'

gcc/ChangeLog:

	* config/riscv/riscv.md: Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/fsflags.c: New test.
---
 gcc/config/riscv/riscv.md                |  8 +++++---
 gcc/testsuite/gcc.target/riscv/fsflags.c | 16 ++++++++++++++++
 2 files changed, 21 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/fsflags.c

Comments

Kito Cheng July 25, 2023, 11 a.m. UTC | #1 
Jin Ma via Gcc-patches <gcc-patches@gcc.gnu.org> 於 2023年7月25日 週二 15:29 寫道：

> The pattern mistakenly believes that fsflags can use immediate numbers,
> but in fact it does not support it. Immediate numbers should use fsflagsi.
>
> For example:
> __builtin_riscv_fsflags(4);
>
> The following error occurred.
> /tmp/ccoWdWqT.s: Assembler messages:
> /tmp/ccoWdWqT.s:14: Error: illegal operands `fsflags 4'
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.md: Likewise.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/fsflags.c: New test.
> ---
>  gcc/config/riscv/riscv.md                |  8 +++++---
>  gcc/testsuite/gcc.target/riscv/fsflags.c | 16 ++++++++++++++++
>  2 files changed, 21 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/fsflags.c
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 4615e811947..1ec85e30d7e 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -3074,7 +3074,7 @@ (define_insn "riscv_frcsr"
>    "frcsr\t%0")
>
>  (define_insn "riscv_fscsr"
> -  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")]
> UNSPECV_FSCSR)]
> +  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "r")]
> UNSPECV_FSCSR)]
>    "TARGET_HARD_FLOAT || TARGET_ZFINX"
>    "fscsr\t%0")
>
> @@ -3085,9 +3085,11 @@ (define_insn "riscv_frflags"
>    "frflags\t%0")
>
>  (define_insn "riscv_fsflags"
> -  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")]
> UNSPECV_FSFLAGS)]
> +  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "r,K")]
> UNSPECV_FSFLAGS)]
>    "TARGET_HARD_FLOAT || TARGET_ZFINX"
> -  "fsflags\t%0")
> +  "@
> +   fsflags\t%0
> +   fsflagsi\t%0")
>

You can be use fsflags%i0, you can reference addsi pattern.


>  (define_insn "*riscv_fsnvsnan<mode>2"
>    [(unspec_volatile [(match_operand:ANYF 0 "register_operand" "f")
> diff --git a/gcc/testsuite/gcc.target/riscv/fsflags.c
> b/gcc/testsuite/gcc.target/riscv/fsflags.c
> new file mode 100644
> index 00000000000..74a97b8a7c7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/fsflags.c
> @@ -0,0 +1,16 @@
> +/* Verify that fsflags is using the correct register or immediate.  */
> +/* { dg-do compile } */
> +/* { dg-require-effective-target hard_float } */
> +/* { dg-options "-O" } */
> +
> +void foo1 (int a)
> +{
> +   __builtin_riscv_fsflags(a);
> +}
> +void foo2 ()
> +{
> +   __builtin_riscv_fsflags(4);
> +}
> +
> +/* { dg-final { scan-assembler-times "fsflags\t" 1 } } */
> +/* { dg-final { scan-assembler-times "fsflagsi\t" 1 } } */
> --
> 2.17.1
>
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4615e811947..1ec85e30d7e 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3074,7 +3074,7 @@  (define_insn "riscv_frcsr"
   "frcsr\t%0")
 
 (define_insn "riscv_fscsr"
-  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSCSR)]
+  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "r")] UNSPECV_FSCSR)]
   "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fscsr\t%0")
 
@@ -3085,9 +3085,11 @@  (define_insn "riscv_frflags"
   "frflags\t%0")
 
 (define_insn "riscv_fsflags"
-  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)]
+  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "r,K")] UNSPECV_FSFLAGS)]
   "TARGET_HARD_FLOAT || TARGET_ZFINX"
-  "fsflags\t%0")
+  "@
+   fsflags\t%0
+   fsflagsi\t%0")
 
 (define_insn "*riscv_fsnvsnan<mode>2"
   [(unspec_volatile [(match_operand:ANYF 0 "register_operand" "f")
diff --git a/gcc/testsuite/gcc.target/riscv/fsflags.c b/gcc/testsuite/gcc.target/riscv/fsflags.c
new file mode 100644
index 00000000000..74a97b8a7c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/fsflags.c
@@ -0,0 +1,16 @@ 
+/* Verify that fsflags is using the correct register or immediate.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target hard_float } */
+/* { dg-options "-O" } */
+
+void foo1 (int a)
+{
+   __builtin_riscv_fsflags(a);
+}
+void foo2 ()
+{
+   __builtin_riscv_fsflags(4);
+}
+
+/* { dg-final { scan-assembler-times "fsflags\t" 1 } } */
+/* { dg-final { scan-assembler-times "fsflagsi\t" 1 } } */