diff mbox series

RISC-V: Fixbug for fsflags instruction error using immediate.

Message ID 20230725063910.1568-1-jinma@linux.alibaba.com
State Unresolved
Headers
Series RISC-V: Fixbug for fsflags instruction error using immediate. |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Jin Ma July 25, 2023, 6:39 a.m. UTC 
  The pattern mistakenly believes that fsflags can use immediate numbers,
but in fact it does not support it. Immediate numbers should use fsflagsi.

For example:
__builtin_riscv_fsflags(4);

The following error occurred:
/tmp/ccoWdWqT.s: Assembler messages:
/tmp/ccoWdWqT.s:14: Error: illegal operands `fsflags 4'

gcc/ChangeLog:

	* config/riscv/riscv.md: Likewise.
---
 gcc/config/riscv/riscv.md | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

Comments

Robin Dapp July 25, 2023, 6:48 a.m. UTC | #1 
Hi Jin,

this looks reasonable.  Would you mind adding (small) test cases
still to make sure we don't accidentally reintroduce the problem?

Regards
 Robin
Jin Ma July 25, 2023, 7:32 a.m. UTC | #2 
> Hi Jin,
> 
> this looks reasonable.  Would you mind adding (small) test cases
> still to make sure we don't accidentally reintroduce the problem?
> 
> Regards
>  Robin

Ok, I have already sent the v2 version, please review it again, thanks.

Link:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625390.html
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4615e811947..1ec85e30d7e 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3074,7 +3074,7 @@  (define_insn "riscv_frcsr"
   "frcsr\t%0")
 
 (define_insn "riscv_fscsr"
-  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSCSR)]
+  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "r")] UNSPECV_FSCSR)]
   "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fscsr\t%0")
 
@@ -3085,9 +3085,11 @@  (define_insn "riscv_frflags"
   "frflags\t%0")
 
 (define_insn "riscv_fsflags"
-  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)]
+  [(unspec_volatile [(match_operand:SI 0 "csr_operand" "r,K")] UNSPECV_FSFLAGS)]
   "TARGET_HARD_FLOAT || TARGET_ZFINX"
-  "fsflags\t%0")
+  "@
+   fsflags\t%0
+   fsflagsi\t%0")
 
 (define_insn "*riscv_fsnvsnan<mode>2"
   [(unspec_volatile [(match_operand:ANYF 0 "register_operand" "f")