From patchwork Tue Jul 18 02:49:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 121735 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1471105vqt; Mon, 17 Jul 2023 19:50:45 -0700 (PDT) X-Google-Smtp-Source: APBJJlEzJh8fqtHEAQuesRcB/eiVO9fG4xtUoB+ycRSDYPihYkMrgV4Q6fRBeC7pA5VPOd50WEa2 X-Received: by 2002:a17:906:c205:b0:986:d833:3cf9 with SMTP id d5-20020a170906c20500b00986d8333cf9mr10618039ejz.39.1689648645722; Mon, 17 Jul 2023 19:50:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689648645; cv=none; d=google.com; s=arc-20160816; b=ARjw0VTtpWFPN9/XaQrWfDxpqWUf8tpaXcFcTbtwn0dQhxFIZg0Ue0QO6HoCszoj6y 6m8hm0w8Hx0Yh6f8CH2tXBbtYpB7WJY6RxTCmarQijtSqX9+Wk7pyu7HlJzuP5CyJImR T+z4A440SX3OPY3AdUnMcBHEVFJI6ohm5yoClF0J1MMrS5vXvMLtQVFvWelyyBv8xf8M jdlcIKc+DxEwdb2SwCM+BFThYgSk0t6SNvpSQmq3zjOX2rFaTIMigFObIPXPCgjBnxfL uzN9lHTlUq6OCOVGd7y/9TWu2FzWSUVYAJ+77+fArlRX/OIhF+tbEz3ZtvdfDLIp3V2R igpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=S0oFt/kXBV3dGbHp1JPHTKeVpx8ZURR9dddFWnzB4R4=; fh=9EZcvfVI324lLsRm78AR5trG4A9hqVpSpoTtyXFX1N4=; b=dim/aKf5N7ATmdKX/hmxKNYpDkAnRzxUzEYqONFF/RD1rCTz1kIR3AssRmHzoLVhHi Dz+G6WC+QRrfE3DWMfNv3BnHXQltwDWdkVMSYa15rrdi6BD+at+JKkrx2r7a/stV1mnZ uz2LyqVjutgdi8KX4+YN1vaA3rzaIVMuZ5sRcOa4cug2xxpJTPfOes+0Gbc5UyrhQS+Q Fe+IxeS1f7YGTJ7wFhyWPGBFl3W8IvWHwDnDD6O45lG65IVX6dWjnXJRF4+FWNASZe6r p1HQ6NnMVWJ6COL3mGjiQq69hk5gCb2KwG4fSny5LzFtpVYe0nNzx7n3XtZ6UHkQp0lU LHPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=nZZ4ZpQS; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id qn17-20020a170907211100b00992bf74c316si494852ejb.974.2023.07.17.19.50.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 19:50:45 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=nZZ4ZpQS; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 88B41385782B for ; Tue, 18 Jul 2023 02:50:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 88B41385782B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689648644; bh=S0oFt/kXBV3dGbHp1JPHTKeVpx8ZURR9dddFWnzB4R4=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=nZZ4ZpQSrc++2ziPAzMq9JXjejBWEDxEMp00S9DuOIqs6Hf4AX0bYWUAiP4nHQzUI hJOHssQNZRgF0ZPxNgm3AWAUcux4DcA/+7Q2Z1bVug942Ktyzv8apQzHNOaK86a7jc ecO5kr3JOqiWwicwVG+S6ep/J/fAwJ1+RvIemKMg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 462003858D20 for ; Tue, 18 Jul 2023 02:50:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 462003858D20 X-IronPort-AV: E=McAfee;i="6600,9927,10774"; a="363554802" X-IronPort-AV: E=Sophos;i="6.01,213,1684825200"; d="scan'208";a="363554802" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2023 19:49:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10774"; a="673746286" X-IronPort-AV: E=Sophos;i="6.01,213,1684825200"; d="scan'208";a="673746286" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 17 Jul 2023 19:49:55 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id C9119100516B; Tue, 18 Jul 2023 10:49:54 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v2] RISC-V: Fix RVV frm run test failure on RV32 Date: Tue, 18 Jul 2023 10:49:53 +0800 Message-Id: <20230718024953.1343484-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230714132050.2728477-1-pan2.li@intel.com> References: <20230714132050.2728477-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771402334416991886 X-GMAIL-MSGID: 1771725018484350236 From: Pan Li Refine the run test case to avoid interactive checking in RV32, by separating each checks in different functions. Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix run failure. Signed-off-by: Pan Li --- .../riscv/rvv/base/float-point-frm-run-1.c | 59 +++++++++++-------- 1 file changed, 36 insertions(+), 23 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c index 245ce7d1fc0..1b2789a924b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c @@ -5,6 +5,24 @@ #include #include +#define DEFINE_TEST_FUNC(FRM) \ +vfloat32m1_t __attribute__ ((noinline)) \ +test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) \ +{ \ + vfloat32m1_t result; \ + \ + set_frm (0); \ + \ + result = __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl); \ + \ + assert_equal (FRM, get_frm (), "The value of frm should be " #FRM "."); \ + \ + return result; \ +} + +#define RUN_TEST_FUNC(FRM, op1, op2, vl) \ + test_float_point_frm_run_##FRM (op1, op2, vl) + static int get_frm () { @@ -41,28 +59,11 @@ assert_equal (int a, int b, char *message) } } -vfloat32m1_t __attribute__ ((noinline)) -test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) -{ - vfloat32m1_t result; - - result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl); - assert_equal (1, get_frm (), "The value of frm register should be 1."); - - result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl); - assert_equal (2, get_frm (), "The value of frm register should be 2."); - - result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); - assert_equal (3, get_frm (), "The value of frm register should be 3."); - - result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); - assert_equal (4, get_frm (), "The value of frm register should be 4."); - - result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl); - assert_equal (0, get_frm (), "The value of frm register should be 0."); - - return result; -} +DEFINE_TEST_FUNC (0) +DEFINE_TEST_FUNC (1) +DEFINE_TEST_FUNC (2) +DEFINE_TEST_FUNC (3) +DEFINE_TEST_FUNC (4) int main () @@ -72,8 +73,20 @@ main () vfloat32m1_t op2; set_frm (4); - test_float_point_frm_run (op1, op2, vl); + RUN_TEST_FUNC (0, op1, op2, vl); + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + RUN_TEST_FUNC (1, op1, op2, vl); + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + RUN_TEST_FUNC (2, op1, op2, vl); + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + RUN_TEST_FUNC (3, op1, op2, vl); + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + RUN_TEST_FUNC (4, op1, op2, vl); assert_equal (4, get_frm (), "The value of frm register should be 4."); return 0;