From patchwork Mon Jul 17 14:42:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 121380 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c923:0:b0:3e4:2afc:c1 with SMTP id j3csp1155067vqt; Mon, 17 Jul 2023 07:43:17 -0700 (PDT) X-Google-Smtp-Source: APBJJlHbpzCFJxIw9n/4ngXn3MyHN49upN8yULrPmTPGUx/3W9q1WhQbJ00ztda9Vu9auWCdIqFS X-Received: by 2002:a17:907:506:b0:98c:df38:517b with SMTP id wj6-20020a170907050600b0098cdf38517bmr9875538ejb.33.1689604997299; Mon, 17 Jul 2023 07:43:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689604997; cv=none; d=google.com; s=arc-20160816; b=c0c8kEz9U/dn1MscX0yh5qtdnzpTMsonNVeC6acDRqwz6LOOYwr222YhFNkVuSOS8G TqT/8ByjxpWieSxEZo+h0t6tlT3nE7KGTFpIBr4vPBTcfqZp9qEvEnjlr2Mr9jqDK9xa +uvUEGkKyeKYepzanl7KLujncu/9Hc6f2pK5gbOzAi5iNo/809KgCD/2M8PZlKwCW/OX tEZc0l8ZUX/AY/drP0hCWK5mExHopUV6iVyuSd40lmyx68TXYEh/toSCLkdkW/Ng60gN 1lpw6OgUBx8y3RlsWyRcelILv/diHXXILq/gG8ROkmwlQytpTWYfA1U0VFdl2mJwfjcb l1Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=Imz9F+XMcyjLSPpHcfCMgyDYVxKeIHHVwO65BH3i0wg=; fh=qt0CWp93fcVd2nwqLpQ5lZ+7OElzl2k5VF5IURKKoXI=; b=EXOPOcSeS8pWIvoa/3wsfz3vz/mF2slrj/zZcMdAnApVzM+KHKI2O3Mg/emSsvtEpB bkpLgpIkHMCQzSu9pZLqcuQRsEy4c41Xyy7ZcqCsUs19LV5ycfwy4Yech8ZsE3xUsiYO N65lF/Nu80wW+9CaczLhTGhh0npW56/ZnyTQHxMZC7srQPwkYIsUwazrJU5nkR0USiL1 N1WhwPZM87D6xlrXx0By1tcgL5L0EXXd9+Yh0N02dJhTuNpjoQlOdT4pxJFB1Y65iEr/ 2N/2cS87njzuW4JcQsRMeEM6VI/z0KlB1sEpvJXCUPzUi41zI1qizwHG0Oohb8nBzoFn asvg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id j22-20020a170906411600b0099396547003si13172348ejk.774.2023.07.17.07.43.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 07:43:17 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A87FE3858C20 for ; Mon, 17 Jul 2023 14:43:00 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id DF68B3858D28 for ; Mon, 17 Jul 2023 14:42:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DF68B3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp90t1689604931t8krj9a8 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 17 Jul 2023 22:42:10 +0800 (CST) X-QQ-SSF: 01400000000000G0T000000A0000000 X-QQ-FEAT: PS/N6jJLnDac2c7Q4rnC0JCGhFE9xR2c1t+TrKR3xgFX/vuu8XMIzQHyQXQ3P EiKhSu81qL2LRzkAs2aDiGvKM4ydXttEyU7UkkAy4XH/YbnHJ/suzQRwh+4YNvj8Vsh0x6+ OtqfpTtjyIE7SrJD0Y2aAQejzEJqh8HbMTBjpWDCyW4lp8ddmzpgeu32OJG8vbLraXaNtVb rlY+t22RRzgc2HjcpnLSB7tETczgBUHc+Ia1LQBRxZ0JbHt+n8SP2kT5OOT/nMTT7BWcgKp m9AcduKIExxInGIghqh5IGK+5dEN52vqR5xZ3DFhdNZYeDZdpCASH6w8NPug7LOky8mGsVK Bi2WlT7sK1AEvMOS0/K1pCAHp9+dzj8GAG0fw7YRACtrmJFLFStF8kSECz/fWCCKzHDuPAY MBQfu5K0vL8= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 13051916486209819946 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: richard.sandiford@arm.com, Ju-Zhe Zhong Subject: [PATCH V2] RTL_SSA: Relax PHI_MODE in phi_setup Date: Mon, 17 Jul 2023 22:42:09 +0800 Message-Id: <20230717144209.316540-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771679249890644844 X-GMAIL-MSGID: 1771679249890644844 From: Ju-Zhe Zhong Hi, Richard. RISC-V port needs to add a bunch VLS modes (V16QI,V32QI,V64QI,...etc) There are sharing same REG_CLASS with VLA modes (VNx16QI,VNx32QI,...etc) When I am adding those VLS modes, the RTL_SSA initialization in VSETVL PASS (inserted after RA) ICE: rvv.c:13:1: internal compiler error: in partial_subreg_p, at rtl.h:3186 13 | } | ^ 0xf7a5b1 partial_subreg_p(machine_mode, machine_mode) ../../../riscv-gcc/gcc/rtl.h:3186 0x1407616 wider_subreg_mode(machine_mode, machine_mode) ../../../riscv-gcc/gcc/rtl.h:3252 0x2a2c6ff rtl_ssa::combine_modes(machine_mode, machine_mode) ../../../riscv-gcc/gcc/rtl-ssa/internals.inl:677 0x2a2b9a4 rtl_ssa::function_info::simplify_phi_setup(rtl_ssa::phi_info*, rtl_ssa::set_info**, bitmap_head*) ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:146 0x2a2c142 rtl_ssa::function_info::simplify_phis() ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:258 0x2a2b3f0 rtl_ssa::function_info::function_info(function*) ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:51 0x1cebab9 pass_vsetvl::init() ../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4578 0x1cec150 pass_vsetvl::execute(function*) ../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716 The reason is that we have V32QImode (size = [32,0]) which is the mode set as regno_reg_rtx[97] When the PHI input def comes from ENTRY BLOCK (index =0), the def->mode () = V32QImode. But the phi_mode = VNx2QI for example (I use VLA modes intrinsic write the codes). Then combine_modes report ICE. gcc/ChangeLog: * rtl-ssa/internals.inl: Fix when mode1 and mode2 are not ordred. --- gcc/rtl-ssa/internals.inl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/rtl-ssa/internals.inl b/gcc/rtl-ssa/internals.inl index 0a61811289d..e49297c12b3 100644 --- a/gcc/rtl-ssa/internals.inl +++ b/gcc/rtl-ssa/internals.inl @@ -673,6 +673,9 @@ combine_modes (machine_mode mode1, machine_mode mode2) if (mode2 == E_BLKmode) return mode1; + if (!ordered_p (GET_MODE_SIZE (mode1), GET_MODE_SIZE (mode2))) + return BLKmode; + return wider_subreg_mode (mode1, mode2); }