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[8.43.85.97]) by mx.google.com with ESMTPS id d16-20020aa7d690000000b0051e57693d06si13375731edr.307.2023.07.16.23.29.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jul 2023 23:29:15 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9F9853858002 for ; Mon, 17 Jul 2023 06:29:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by sourceware.org (Postfix) with ESMTPS id 88D1C3858D1E for ; Mon, 17 Jul 2023 06:28:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 88D1C3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp76t1689575310tndcy8x5 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 17 Jul 2023 14:28:29 +0800 (CST) X-QQ-SSF: 01400000000000G0T000000A0000000 X-QQ-FEAT: W+onFc5Tw4McFWOBOH9+/1sZs364zWwITx8pPINYwV/sfQg64sDt8j+iX6u4F qr2rMOdTGODtMS44UZbT0jrsuv9jjGUGxCkV+C4yXq3DdShkHd3RCu2bYc0dl0WtR0EgFEe 44IzL/pcVUVmciRE9Dc67W9yfUQPx3zZ69VHrugZ4PAPiHEUYPUj1C6TyBgVVp2HBWIzhIZ NtYqs4CDrarH+3yxuyJsPzzJdhxQ6O8oea4fKPCkatCYLmcZZtAeuWxGarAyz5c0SoLmlil Xt6rCUPm36ftpDuR6Y/rgalHpl20H1drR5RLCEdEBBbnr2JfSogvnIQJgKm5vEOA/25t+cl /Ga5gGV05QXAxy5gTn7uoaXMDkkXto8AYHcJ2ceIGcLwYPKHQXhJ43fmZCqLd3lBFBd7Bto 3rWEf5/OjRI= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 4535990452286414973 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH V2] RISC-V: Add TARGET_MIN_VLEN > 4096 check Date: Mon, 17 Jul 2023 14:28:28 +0800 Message-Id: <20230717062828.47511-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771648167378576444 X-GMAIL-MSGID: 1771648167378576444 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_option_override): Add TARGET_MIN_VLEN < 4096 check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvl-unimplemented.c: New test. --- gcc/config/riscv/riscv.cc | 8 ++++++++ .../gcc.target/riscv/rvv/base/zvl-unimplemented.c | 4 ++++ 2 files changed, 12 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6ed735d6983..432c1ce771e 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6672,6 +6672,14 @@ riscv_option_override (void) riscv_stack_protector_guard_offset = offs; } + /* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of + both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16. + + We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */ + if (riscv_vector_chunks.is_constant () && TARGET_MIN_VLEN > 4096) + sorry ( + "Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension"); + /* Convert -march to a chunks count. */ riscv_vector_chunks = riscv_convert_vector_bits (); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented.c new file mode 100644 index 00000000000..d0e7c8ace3b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv_zvl8192b_zvl256b_zvl512b_zvl1024b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ + +void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" }