diff mbox series

RISC-V: Add TARGET_MIN_VLEN > 4096 check

Message ID 20230717060423.31423-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add TARGET_MIN_VLEN > 4096 check |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai July 17, 2023, 6:04 a.m. UTC 
  gcc/ChangeLog:

        * config/riscv/riscv.cc (riscv_option_override): Report ERROR for TARGET_MIN_VLEN > 4096

---
 gcc/config/riscv/riscv.cc | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Kito Cheng July 17, 2023, 6:12 a.m. UTC | #1 
On Mon, Jul 17, 2023 at 2:05 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.cc (riscv_option_override): Report ERROR for TARGET_MIN_VLEN > 4096
>
> ---
>  gcc/config/riscv/riscv.cc | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 6ed735d6983..ce523eea9ba 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -6672,6 +6672,14 @@ riscv_option_override (void)
>        riscv_stack_protector_guard_offset = offs;
>      }
>
> +  /* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of
> +     both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16.
> +
> +     We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
> +  if (TARGET_MIN_VLEN > 4096)
> +    error (

For this scenario, use sorry rather than error,
and I assume this is only a problem for
-param=riscv-autovec-preference=fixed-vlmax?


> +      "Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension");
> +
>    /* Convert -march to a chunks count.  */
>    riscv_vector_chunks = riscv_convert_vector_bits ();
>  }
> --
> 2.36.1
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6ed735d6983..ce523eea9ba 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6672,6 +6672,14 @@  riscv_option_override (void)
       riscv_stack_protector_guard_offset = offs;
     }
 
+  /* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of
+     both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16.
+
+     We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
+  if (TARGET_MIN_VLEN > 4096)
+    error (
+      "Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension");
+
   /* Convert -march to a chunks count.  */
   riscv_vector_chunks = riscv_convert_vector_bits ();
 }