[gcc-wwwdocs] gcc-13/14: Mention Intel new ISA and march support
Checks
Commit Message
Hi all,
This patch adds documentation to wwwdocs to mention the recent introduction
of Intel new ISA and march.
Ok for trunk?
BRs,
Haochen
---
htdocs/gcc-13/changes.html | 4 ++++
htdocs/gcc-14/changes.html | 34 +++++++++++++++++++++++++++++++++-
2 files changed, 37 insertions(+), 1 deletion(-)
Comments
On Mon, Jul 17, 2023 at 5:34 AM Haochen Jiang via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Hi all,
>
> This patch adds documentation to wwwdocs to mention the recent introduction
> of Intel new ISA and march.
>
> Ok for trunk?
OK.
> BRs,
> Haochen
>
> ---
> htdocs/gcc-13/changes.html | 4 ++++
> htdocs/gcc-14/changes.html | 34 +++++++++++++++++++++++++++++++++-
> 2 files changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
> index 39414e18..68e8c5cc 100644
> --- a/htdocs/gcc-13/changes.html
> +++ b/htdocs/gcc-13/changes.html
> @@ -593,6 +593,10 @@ You may also want to check out our
> </li>
> <li>GCC now supports the Intel CPU named Granite Rapids through
> <code>-march=graniterapids</code>.
> + The switch enables the AMX-FP16, PREFETCHI ISA extensions.
> + </li>
> + <li>GCC now supports the Intel CPU named Granite Rapids D through
> + <code>-march=graniterapids-d</code>.
> The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions.
> </li>
> <li>GCC now supports AMD CPUs based on the <code>znver4</code> core
> diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
> index 3f797642..dad1ba53 100644
> --- a/htdocs/gcc-14/changes.html
> +++ b/htdocs/gcc-14/changes.html
> @@ -108,7 +108,39 @@ a work-in-progress.</p>
>
> <!-- <h3 id="avr">AVR</h3> -->
>
> -<!-- <h3 id="x86">IA-32/x86-64</h3> -->
> +<h3 id="x86">IA-32/x86-64</h3>
> +<ul>
> + <li>New ISA extension support for Intel AVX-VNNI-INT16 was added.
> + AVX-VNNI-INT16 intrinsics are available via the <code>-mavxvnniint16</code>
> + compiler switch.
> + </li>
> + <li>New ISA extension support for Intel SHA512 was added.
> + SHA512 intrinsics are available via the <code>-msha512</code>
> + compiler switch.
> + </li>
> + <li>New ISA extension support for Intel SM3 was added.
> + SM3 intrinsics are available via the <code>-msm3</code>
> + compiler switch.
> + </li>
> + <li>New ISA extension support for Intel SM4 was added.
> + SM4 intrinsics are available via the <code>-msm4</code>
> + compiler switch.
> + </li>
> + <li>GCC now supports the Intel CPU named Arrow Lake through
> + <code>-march=arrowlake</code>.
> + Based on Alder Lake, the switch further enables the AVX-IFMA,
> + AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions.
> + </li>
> + <li>GCC now supports the Intel CPU named Arrow Lake S through
> + <code>-march=arrowlake-s</code>.
> + Based on Arrow Lake, the switch further enables the AVX-VNNI-INT16, SHA512,
> + SM3 and SM4 ISA extensions.
> + </li>
> + <li>GCC now supports the Intel CPU named Lunar Lake through
> + <code>-march=lunarlake</code>.
> + Lunar Lake is based on Arrow Lake S.
> + </li>
> +</ul>
>
> <!-- <h3 id="mips">MIPS</h3> -->
>
> --
> 2.31.1
>
> -----Original Message-----
> From: Gcc-patches <gcc-patches-
> bounces+haochen.jiang=intel.com@gcc.gnu.org> On Behalf Of Haochen Jiang
> via Gcc-patches
> Sent: Monday, July 17, 2023 11:34 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Liu, Hongtao <hongtao.liu@intel.com>; ubizjak@gmail.com
> Subject: [PATCH] [gcc-wwwdocs]gcc-13/14: Mention Intel new ISA and march
> support
>
> Hi all,
>
> This patch adds documentation to wwwdocs to mention the recent
> introduction of Intel new ISA and march.
>
> Ok for trunk?
I will commit the patch next Monday if there is no objection.
Thx,
Haochen
>
> BRs,
> Haochen
>
> ---
> htdocs/gcc-13/changes.html | 4 ++++
> htdocs/gcc-14/changes.html | 34
> +++++++++++++++++++++++++++++++++-
> 2 files changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index
> 39414e18..68e8c5cc 100644
> --- a/htdocs/gcc-13/changes.html
> +++ b/htdocs/gcc-13/changes.html
> @@ -593,6 +593,10 @@ You may also want to check out our
> </li>
> <li>GCC now supports the Intel CPU named Granite Rapids through
> <code>-march=graniterapids</code>.
> + The switch enables the AMX-FP16, PREFETCHI ISA extensions.
> + </li>
> + <li>GCC now supports the Intel CPU named Granite Rapids D through
> + <code>-march=graniterapids-d</code>.
> The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA
> extensions.
> </li>
> <li>GCC now supports AMD CPUs based on the <code>znver4</code> core
> diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index
> 3f797642..dad1ba53 100644
> --- a/htdocs/gcc-14/changes.html
> +++ b/htdocs/gcc-14/changes.html
> @@ -108,7 +108,39 @@ a work-in-progress.</p>
>
> <!-- <h3 id="avr">AVR</h3> -->
>
> -<!-- <h3 id="x86">IA-32/x86-64</h3> -->
> +<h3 id="x86">IA-32/x86-64</h3>
> +<ul>
> + <li>New ISA extension support for Intel AVX-VNNI-INT16 was added.
> + AVX-VNNI-INT16 intrinsics are available via the <code>-
> mavxvnniint16</code>
> + compiler switch.
> + </li>
> + <li>New ISA extension support for Intel SHA512 was added.
> + SHA512 intrinsics are available via the <code>-msha512</code>
> + compiler switch.
> + </li>
> + <li>New ISA extension support for Intel SM3 was added.
> + SM3 intrinsics are available via the <code>-msm3</code>
> + compiler switch.
> + </li>
> + <li>New ISA extension support for Intel SM4 was added.
> + SM4 intrinsics are available via the <code>-msm4</code>
> + compiler switch.
> + </li>
> + <li>GCC now supports the Intel CPU named Arrow Lake through
> + <code>-march=arrowlake</code>.
> + Based on Alder Lake, the switch further enables the AVX-IFMA,
> + AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions.
> + </li>
> + <li>GCC now supports the Intel CPU named Arrow Lake S through
> + <code>-march=arrowlake-s</code>.
> + Based on Arrow Lake, the switch further enables the AVX-VNNI-INT16,
> SHA512,
> + SM3 and SM4 ISA extensions.
> + </li>
> + <li>GCC now supports the Intel CPU named Lunar Lake through
> + <code>-march=lunarlake</code>.
> + Lunar Lake is based on Arrow Lake S.
> + </li>
> +</ul>
>
> <!-- <h3 id="mips">MIPS</h3> -->
>
> --
> 2.31.1
> -----Original Message-----
> From: Jiang, Haochen <haochen.jiang@intel.com>
> Sent: Friday, October 27, 2023 10:52 AM
> To: Jiang, Haochen <haochen.jiang@intel.com>; gcc-patches@gcc.gnu.org
> Cc: Liu, Hongtao <hongtao.liu@intel.com>; ubizjak@gmail.com; Gerald Pfeifer
> <gerald@pfeifer.com>
> Subject: RE: [PATCH] [gcc-wwwdocs]gcc-13/14: Mention Intel new ISA and
> march support
>
> > -----Original Message-----
> > From: Gcc-patches <gcc-patches-
> > bounces+haochen.jiang=intel.com@gcc.gnu.org> On Behalf Of Haochen
> > bounces+Jiang
> > via Gcc-patches
> > Sent: Monday, July 17, 2023 11:34 AM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Liu, Hongtao <hongtao.liu@intel.com>; ubizjak@gmail.com
> > Subject: [PATCH] [gcc-wwwdocs]gcc-13/14: Mention Intel new ISA and
> > march support
> >
> > Hi all,
> >
> > This patch adds documentation to wwwdocs to mention the recent
> > introduction of Intel new ISA and march.
> >
> > Ok for trunk?
>
> I will commit the patch next Monday if there is no objection.
Sorry for the disturb since I find the wrong mail to reply because they
are too similar.
>
> Thx,
> Haochen
>
> >
> > BRs,
> > Haochen
> >
> > ---
> > htdocs/gcc-13/changes.html | 4 ++++
> > htdocs/gcc-14/changes.html | 34
> > +++++++++++++++++++++++++++++++++-
> > 2 files changed, 37 insertions(+), 1 deletion(-)
> >
> > diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
> > index 39414e18..68e8c5cc 100644
> > --- a/htdocs/gcc-13/changes.html
> > +++ b/htdocs/gcc-13/changes.html
> > @@ -593,6 +593,10 @@ You may also want to check out our
> > </li>
> > <li>GCC now supports the Intel CPU named Granite Rapids through
> > <code>-march=graniterapids</code>.
> > + The switch enables the AMX-FP16, PREFETCHI ISA extensions.
> > + </li>
> > + <li>GCC now supports the Intel CPU named Granite Rapids D through
> > + <code>-march=graniterapids-d</code>.
> > The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA
> > extensions.
> > </li>
> > <li>GCC now supports AMD CPUs based on the <code>znver4</code> core
> > diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
> > index
> > 3f797642..dad1ba53 100644
> > --- a/htdocs/gcc-14/changes.html
> > +++ b/htdocs/gcc-14/changes.html
> > @@ -108,7 +108,39 @@ a work-in-progress.</p>
> >
> > <!-- <h3 id="avr">AVR</h3> -->
> >
> > -<!-- <h3 id="x86">IA-32/x86-64</h3> -->
> > +<h3 id="x86">IA-32/x86-64</h3>
> > +<ul>
> > + <li>New ISA extension support for Intel AVX-VNNI-INT16 was added.
> > + AVX-VNNI-INT16 intrinsics are available via the <code>-
> > mavxvnniint16</code>
> > + compiler switch.
> > + </li>
> > + <li>New ISA extension support for Intel SHA512 was added.
> > + SHA512 intrinsics are available via the <code>-msha512</code>
> > + compiler switch.
> > + </li>
> > + <li>New ISA extension support for Intel SM3 was added.
> > + SM3 intrinsics are available via the <code>-msm3</code>
> > + compiler switch.
> > + </li>
> > + <li>New ISA extension support for Intel SM4 was added.
> > + SM4 intrinsics are available via the <code>-msm4</code>
> > + compiler switch.
> > + </li>
> > + <li>GCC now supports the Intel CPU named Arrow Lake through
> > + <code>-march=arrowlake</code>.
> > + Based on Alder Lake, the switch further enables the AVX-IFMA,
> > + AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions.
> > + </li>
> > + <li>GCC now supports the Intel CPU named Arrow Lake S through
> > + <code>-march=arrowlake-s</code>.
> > + Based on Arrow Lake, the switch further enables the
> > + AVX-VNNI-INT16,
> > SHA512,
> > + SM3 and SM4 ISA extensions.
> > + </li>
> > + <li>GCC now supports the Intel CPU named Lunar Lake through
> > + <code>-march=lunarlake</code>.
> > + Lunar Lake is based on Arrow Lake S.
> > + </li>
> > +</ul>
> >
> > <!-- <h3 id="mips">MIPS</h3> -->
> >
> > --
> > 2.31.1
On Mon, 17 Jul 2023, Haochen Jiang via Gcc-patches wrote:
> <li>GCC now supports the Intel CPU named Granite Rapids through
> <code>-march=graniterapids</code>.
> + The switch enables the AMX-FP16, PREFETCHI ISA extensions.
Do I understand correclty that it enables AMX-FP16 and PREFETCHI?
How about changing this to use "and", as in
"The switch enables the AMX-FP16, PREFETCHI ISA extensions."
?
Let me know, and I can make the change.
Gerald
> -----Original Message-----
> From: Gerald Pfeifer <gerald@pfeifer.com>
> Sent: Saturday, November 25, 2023 7:29 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao <hongtao.liu@intel.com>;
> ubizjak@gmail.com
> Subject: Re: [PATCH] [gcc-wwwdocs]gcc-13/14: Mention Intel new ISA and march
> support
>
> On Mon, 17 Jul 2023, Haochen Jiang via Gcc-patches wrote:
> > <li>GCC now supports the Intel CPU named Granite Rapids through
> > <code>-march=graniterapids</code>.
> > + The switch enables the AMX-FP16, PREFETCHI ISA extensions.
>
> Do I understand correclty that it enables AMX-FP16 and PREFETCHI?
>
> How about changing this to use "and", as in
> "The switch enables the AMX-FP16, PREFETCHI ISA extensions."
> ?
>
> Let me know, and I can make the change.
>
Ok for me.
Thx,
Haochen
> Gerald
On Mon, 27 Nov 2023, Jiang, Haochen wrote:
>> How about changing this to use "and", as in
>> "The switch enables the AMX-FP16, PREFETCHI ISA extensions."
>> ?
> Ok for me.
Done and pushed thusly.
Gerald
commit 617a25d7d89a9cce121e85b693eed1ee3f94354b
Author: Gerald Pfeifer <gerald@pfeifer.com>
Date: Wed Dec 13 13:43:39 2023 +0800
gcc-13: Refine noteo on -march=graniterapids
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 8ef3d639..ee6383a0 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -593,7 +593,7 @@ You may also want to check out our
</li>
<li>GCC now supports the Intel CPU named Granite Rapids through
<code>-march=graniterapids</code>.
- The switch enables the AMX-FP16, PREFETCHI ISA extensions.
+ The switch enables the AMX-FP16 and PREFETCHI ISA extensions.
</li>
<li>GCC now supports the Intel CPU named Granite Rapids D through
<code>-march=graniterapids-d</code>.
@@ -593,6 +593,10 @@ You may also want to check out our
</li>
<li>GCC now supports the Intel CPU named Granite Rapids through
<code>-march=graniterapids</code>.
+ The switch enables the AMX-FP16, PREFETCHI ISA extensions.
+ </li>
+ <li>GCC now supports the Intel CPU named Granite Rapids D through
+ <code>-march=graniterapids-d</code>.
The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions.
</li>
<li>GCC now supports AMD CPUs based on the <code>znver4</code> core
@@ -108,7 +108,39 @@ a work-in-progress.</p>
<!-- <h3 id="avr">AVR</h3> -->
-<!-- <h3 id="x86">IA-32/x86-64</h3> -->
+<h3 id="x86">IA-32/x86-64</h3>
+<ul>
+ <li>New ISA extension support for Intel AVX-VNNI-INT16 was added.
+ AVX-VNNI-INT16 intrinsics are available via the <code>-mavxvnniint16</code>
+ compiler switch.
+ </li>
+ <li>New ISA extension support for Intel SHA512 was added.
+ SHA512 intrinsics are available via the <code>-msha512</code>
+ compiler switch.
+ </li>
+ <li>New ISA extension support for Intel SM3 was added.
+ SM3 intrinsics are available via the <code>-msm3</code>
+ compiler switch.
+ </li>
+ <li>New ISA extension support for Intel SM4 was added.
+ SM4 intrinsics are available via the <code>-msm4</code>
+ compiler switch.
+ </li>
+ <li>GCC now supports the Intel CPU named Arrow Lake through
+ <code>-march=arrowlake</code>.
+ Based on Alder Lake, the switch further enables the AVX-IFMA,
+ AVX-VNNI-INT8, AVX-NE-CONVERT and CMPccXADD ISA extensions.
+ </li>
+ <li>GCC now supports the Intel CPU named Arrow Lake S through
+ <code>-march=arrowlake-s</code>.
+ Based on Arrow Lake, the switch further enables the AVX-VNNI-INT16, SHA512,
+ SM3 and SM4 ISA extensions.
+ </li>
+ <li>GCC now supports the Intel CPU named Lunar Lake through
+ <code>-march=lunarlake</code>.
+ Lunar Lake is based on Arrow Lake S.
+ </li>
+</ul>
<!-- <h3 id="mips">MIPS</h3> -->