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[8.43.85.97]) by mx.google.com with ESMTPS id n26-20020a170906119a00b00992d6e88081si7439814eja.956.2023.07.13.03.26.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 03:26:41 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="D8Dry+7/"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5344F385C6F4 for ; Thu, 13 Jul 2023 10:25:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5344F385C6F4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689243928; bh=iKVHb3jApXLii0k4vJsTYRkrU2NU5DhCdEOr3Jy+oVI=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=D8Dry+7/kexKZBm5IWYsWPmR+LHiA9nl/6wCbtH4pcechpEc6Jv4++xycbgY1opHV xL0DU3zAxw7gl0tIuWh9Z+WpLdamItqlBy8iYbhmr7kK0zjYfAFMyB6TwvgkLejbwf EaFGih1v6TPaAxAuFdSirb0iIlUo5P9ga4DsQkvU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-oi1-x22d.google.com (mail-oi1-x22d.google.com [IPv6:2607:f8b0:4864:20::22d]) by sourceware.org (Postfix) with ESMTPS id 3D115385828E for ; Thu, 13 Jul 2023 10:22:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3D115385828E Received: by mail-oi1-x22d.google.com with SMTP id 5614622812f47-3a1ebb85f99so546275b6e.2 for ; Thu, 13 Jul 2023 03:22:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689243751; x=1691835751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iKVHb3jApXLii0k4vJsTYRkrU2NU5DhCdEOr3Jy+oVI=; b=l4GNMPQuv554Ln3iEv+1m4iXfncE4o99KQN0OA4Y+I0RBaWGt9VOr6dtoDlH23lY8M nkBYlbyS/rgy2llQgGD+5d8A7Uf65WPGS9ETn14s76gMVD0VzawBgB8uzLDA99kNyfJG XYJ/SKuxHvp5iPp+RvLF2PKoJMaBM/zYzkiwDcLDup+iy4MHYPIeaWKrZM6vRkAdw7qI ltKx+zAeajIKtoq6oABO0C8oiseep6AUf017+y+GKKEaV53D2pL6qbje3Jk8mP03XgbF bnjA6z5Xw1GAoxLwUh6ArNJBfamQj+OCllHHidXiJCji/ghyWT9laTSjbwfysdJx+ns2 jD4A== X-Gm-Message-State: ABy/qLa8SOH0JBvyomsyE9I1X7BVyjUPWuJMqzv3+Iiug2JoTZdYddV+ 3o4GXo6mZRyydKLRdo9Nq3creBUwZVm/8bItRqB8+rAK X-Received: by 2002:aca:bc45:0:b0:3a0:3773:f294 with SMTP id m66-20020acabc45000000b003a03773f294mr1442903oif.8.1689243751266; Thu, 13 Jul 2023 03:22:31 -0700 (PDT) Received: from localhost.localdomain ([139.178.84.207]) by smtp.gmail.com with ESMTPSA id a9-20020a05680802c900b003a020d24d7dsm2707263oid.56.2023.07.13.03.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 03:22:30 -0700 (PDT) To: gcc-patches@gcc.gnu.org, Kyrylo.Tkachov@arm.com, richard.earnshaw@arm.com, richard.sandiford@arm.com Cc: Christophe Lyon Subject: [PATCH 3/6] arm: [MVE intrinsics factorize vcmulq Date: Thu, 13 Jul 2023 10:22:21 +0000 Message-Id: <20230713102224.1161596-3-christophe.lyon@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230713102224.1161596-1-christophe.lyon@linaro.org> References: <20230713102224.1161596-1-christophe.lyon@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771300718387464471 X-GMAIL-MSGID: 1771300718387464471 Factorize vcmulq builtins so that they use parameterized names. We can merged them with vcadd. 2023-07-13 Christophe Lyon gcc/: * config/arm/arm_mve_builtins.def (vcmulq_rot90_f) (vcmulq_rot270_f, vcmulq_rot180_f, vcmulq_f): Add "_f" suffix. * config/arm/iterators.md (MVE_VCADDQ_VCMULQ) (MVE_VCADDQ_VCMULQ_M): New. (mve_insn): Add vcmul. (rot): Add VCMULQ_M_F, VCMULQ_ROT90_M_F, VCMULQ_ROT180_M_F, VCMULQ_ROT270_M_F. (VCMUL): Delete. (mve_rot): Add VCMULQ_M_F, VCMULQ_ROT90_M_F, VCMULQ_ROT180_M_F, VCMULQ_ROT270_M_F. * config/arm/mve.md (mve_vcmulq): Merge into @mve_q_f. (mve_vcmulq_m_f, mve_vcmulq_rot180_m_f) (mve_vcmulq_rot270_m_f, mve_vcmulq_rot90_m_f): Merge into @mve_q_m_f. --- gcc/config/arm/arm_mve_builtins.def | 8 +-- gcc/config/arm/iterators.md | 27 +++++++-- gcc/config/arm/mve.md | 92 +++-------------------------- 3 files changed, 33 insertions(+), 94 deletions(-) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 63ad1845593..56358c0bd02 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -191,6 +191,10 @@ VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot90_, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot270_, v16qi, v8hi, v4si) VAR2 (BINOP_NONE_NONE_NONE, vcaddq_rot90_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vcaddq_rot270_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot90_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot270_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot180_f, v8hf, v4sf) +VAR2 (BINOP_NONE_NONE_NONE, vcmulq_f, v8hf, v4sf) VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot90_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si) @@ -874,10 +878,6 @@ VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_vec_u, v16qi, v8hi, v4si) VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_carry_u, v16qi, v8hi, v4si) /* optabs without any suffixes. */ -VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot90, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot270, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot180, v8hf, v4sf) -VAR2 (BINOP_NONE_NONE_NONE, vcmulq, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot90, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot270, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_NONE, vcmlaq_rot180, v8hf, v4sf) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index da1ead34e58..9f71404e26c 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -901,8 +901,19 @@ VPSELQ_F ]) +(define_int_iterator MVE_VCADDQ_VCMULQ [ + UNSPEC_VCADD90 UNSPEC_VCADD270 + UNSPEC_VCMUL UNSPEC_VCMUL90 UNSPEC_VCMUL180 UNSPEC_VCMUL270 + ]) + +(define_int_iterator MVE_VCADDQ_VCMULQ_M [ + VCADDQ_ROT90_M_F VCADDQ_ROT270_M_F + VCMULQ_M_F VCMULQ_ROT90_M_F VCMULQ_ROT180_M_F VCMULQ_ROT270_M_F + ]) + (define_int_attr mve_insn [ (UNSPEC_VCADD90 "vcadd") (UNSPEC_VCADD270 "vcadd") + (UNSPEC_VCMUL "vcmul") (UNSPEC_VCMUL90 "vcmul") (UNSPEC_VCMUL180 "vcmul") (UNSPEC_VCMUL270 "vcmul") (VABAVQ_P_S "vabav") (VABAVQ_P_U "vabav") (VABAVQ_S "vabav") (VABAVQ_U "vabav") (VABDQ_M_S "vabd") (VABDQ_M_U "vabd") (VABDQ_M_F "vabd") @@ -931,6 +942,7 @@ (VCLSQ_M_S "vcls") (VCLSQ_S "vcls") (VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz") + (VCMULQ_M_F "vcmul") (VCMULQ_ROT90_M_F "vcmul") (VCMULQ_ROT180_M_F "vcmul") (VCMULQ_ROT270_M_F "vcmul") (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate") (VDUPQ_M_N_S "vdup") (VDUPQ_M_N_U "vdup") (VDUPQ_M_N_F "vdup") (VDUPQ_N_S "vdup") (VDUPQ_N_U "vdup") (VDUPQ_N_F "vdup") @@ -2182,7 +2194,11 @@ (UNSPEC_VCMLA "0") (UNSPEC_VCMLA90 "90") (UNSPEC_VCMLA180 "180") - (UNSPEC_VCMLA270 "270")]) + (UNSPEC_VCMLA270 "270") + (VCMULQ_M_F "0") + (VCMULQ_ROT90_M_F "90") + (VCMULQ_ROT180_M_F "180") + (VCMULQ_ROT270_M_F "270")]) ;; The complex operations when performed on a real complex number require two ;; instructions to perform the operation. e.g. complex multiplication requires @@ -2230,10 +2246,11 @@ (UNSPEC_VCMUL "") (UNSPEC_VCMUL90 "_rot90") (UNSPEC_VCMUL180 "_rot180") - (UNSPEC_VCMUL270 "_rot270")]) - -(define_int_iterator VCMUL [UNSPEC_VCMUL UNSPEC_VCMUL90 - UNSPEC_VCMUL180 UNSPEC_VCMUL270]) + (UNSPEC_VCMUL270 "_rot270") + (VCMULQ_M_F "") + (VCMULQ_ROT90_M_F "_rot90") + (VCMULQ_ROT180_M_F "_rot180") + (VCMULQ_ROT270_M_F "_rot270")]) (define_int_attr fcmac1 [(UNSPEC_VCMLA "a") (UNSPEC_VCMLA_CONJ "a") (UNSPEC_VCMLA180 "s") (UNSPEC_VCMLA180_CONJ "s")]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index a6db6d1b81d..0b99bf017dc 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1212,13 +1212,14 @@ ;; ;; [vcaddq_rot90_f, vcaddq_rot270_f] +;; [vcmulq, vcmulq_rot90, vcmulq_rot180, vcmulq_rot270] ;; (define_insn "@mve_q_f" [ (set (match_operand:MVE_0 0 "s_register_operand" "") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w")] - VCADD)) + MVE_VCADDQ_VCMULQ)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" ".f%#\t%q0, %q1, %q2, #" @@ -1254,21 +1255,6 @@ [(set_attr "type" "mve_move") ]) -;; -;; [vcmulq, vcmulq_rot90, vcmulq_rot180, vcmulq_rot270]) -;; -(define_insn "mve_vcmulq" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMUL)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmul.f%# %q0, %q1, %q2, #" - [(set_attr "type" "mve_move") -]) - ;; ;; [vctp8q_m vctp16q_m vctp32q_m vctp64q_m]) ;; @@ -3174,6 +3160,10 @@ ;; ;; [vcaddq_rot90_m_f] ;; [vcaddq_rot270_m_f] +;; [vcmulq_m_f] +;; [vcmulq_rot90_m_f] +;; [vcmulq_rot180_m_f] +;; [vcmulq_rot270_m_f] ;; (define_insn "@mve_q_m_f" [ @@ -3182,7 +3172,7 @@ (match_operand:MVE_0 2 "s_register_operand" "w") (match_operand:MVE_0 3 "s_register_operand" "w") (match_operand: 4 "vpr_register_operand" "Up")] - VCADDQ_M_F)) + MVE_VCADDQ_VCMULQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" "vpst\;t.f%#\t%q0, %q2, %q3, #" @@ -3257,74 +3247,6 @@ [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vcmulq_m_f]) -;; -(define_insn "mve_vcmulq_m_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VCMULQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmult.f%# %q0, %q2, %q3, #0" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmulq_rot180_m_f]) -;; -(define_insn "mve_vcmulq_rot180_m_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VCMULQ_ROT180_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmult.f%# %q0, %q2, %q3, #180" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmulq_rot270_m_f]) -;; -(define_insn "mve_vcmulq_rot270_m_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VCMULQ_ROT270_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmult.f%# %q0, %q2, %q3, #270" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vcmulq_rot90_m_f]) -;; -(define_insn "mve_vcmulq_rot90_m_f" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand: 4 "vpr_register_operand" "Up")] - VCMULQ_ROT90_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcmult.f%# %q0, %q2, %q3, #90" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vornq_m_f]) ;;