[1/6] arm: [MVE intrinsics] Factorize vcaddq vhcaddq
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Commit Message
Factorize vcaddq, vhcaddq so that they use the same parameterized
names.
To be able to use the same patterns, we add a suffix to vcaddq.
Note that vcadd uses UNSPEC_VCADDxx for builtins without predication,
and VCADDQ_ROTxx_M_x (that is, not starting with "UNSPEC_"). The
UNPEC_* names are also used by neon.md
2023-07-13 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* config/arm/arm_mve_builtins.def (vcaddq_rot90_, vcaddq_rot270_)
(vcaddq_rot90_f, vcaddq_rot90_f): Add "_" or "_f" suffix.
* config/arm/iterators.md (mve_insn): Add vcadd, vhcadd.
(isu): Add UNSPEC_VCADD90, UNSPEC_VCADD270, VCADDQ_ROT270_M_U,
VCADDQ_ROT270_M_S, VCADDQ_ROT90_M_U, VCADDQ_ROT90_M_S,
VHCADDQ_ROT90_M_S, VHCADDQ_ROT270_M_S, VHCADDQ_ROT90_S,
VHCADDQ_ROT270_S.
(rot): Add VCADDQ_ROT90_M_F, VCADDQ_ROT90_M_S, VCADDQ_ROT90_M_U,
VCADDQ_ROT270_M_F, VCADDQ_ROT270_M_S, VCADDQ_ROT270_M_U,
VHCADDQ_ROT90_S, VHCADDQ_ROT270_S, VHCADDQ_ROT90_M_S,
VHCADDQ_ROT270_M_S.
(mve_rot): Add VCADDQ_ROT90_M_F, VCADDQ_ROT90_M_S,
VCADDQ_ROT90_M_U, VCADDQ_ROT270_M_F, VCADDQ_ROT270_M_S,
VCADDQ_ROT270_M_U, VHCADDQ_ROT90_S, VHCADDQ_ROT270_S,
VHCADDQ_ROT90_M_S, VHCADDQ_ROT270_M_S.
(supf): Add VHCADDQ_ROT90_M_S, VHCADDQ_ROT270_M_S,
VHCADDQ_ROT90_S, VHCADDQ_ROT270_S, UNSPEC_VCADD90,
UNSPEC_VCADD270.
(VCADDQ_ROT270_M): Delete.
(VCADDQ_M_F VxCADDQ VxCADDQ_M): New.
(VCADDQ_ROT90_M): Delete.
* config/arm/mve.md (mve_vcaddq<mve_rot><mode>)
(mve_vhcaddq_rot270_s<mode>, mve_vhcaddq_rot90_s<mode>): Merge
into ...
(@mve_<mve_insn>q<mve_rot>_<supf><mode>): ... this.
(mve_vcaddq<mve_rot><mode>): Rename into ...
(@mve_<mve_insn>q<mve_rot>_f<mode>): ... this
(mve_vcaddq_rot270_m_<supf><mode>)
(mve_vcaddq_rot90_m_<supf><mode>, mve_vhcaddq_rot270_m_s<mode>)
(mve_vhcaddq_rot90_m_s<mode>): Merge into ...
(@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): ... this.
(mve_vcaddq_rot270_m_f<mode>, mve_vcaddq_rot90_m_f<mode>): Merge
into ...
(@mve_<mve_insn>q<mve_rot>_m_f<mode>): ... this.
---
gcc/config/arm/arm_mve_builtins.def | 6 +-
gcc/config/arm/iterators.md | 38 +++++++-
gcc/config/arm/mve.md | 135 +++++-----------------------
3 files changed, 62 insertions(+), 117 deletions(-)
Comments
> -----Original Message-----
> From: Christophe Lyon <christophe.lyon@linaro.org>
> Sent: Thursday, July 13, 2023 11:22 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>;
> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Cc: Christophe Lyon <christophe.lyon@linaro.org>
> Subject: [PATCH 1/6] arm: [MVE intrinsics] Factorize vcaddq vhcaddq
>
> Factorize vcaddq, vhcaddq so that they use the same parameterized
> names.
>
> To be able to use the same patterns, we add a suffix to vcaddq.
>
> Note that vcadd uses UNSPEC_VCADDxx for builtins without predication,
> and VCADDQ_ROTxx_M_x (that is, not starting with "UNSPEC_"). The
> UNPEC_* names are also used by neon.md
Thanks for working on this.
The series is ok.
Kyrill
>
> 2023-07-13 Christophe Lyon <christophe.lyon@linaro.org>
>
> gcc/
> * config/arm/arm_mve_builtins.def (vcaddq_rot90_,
> vcaddq_rot270_)
> (vcaddq_rot90_f, vcaddq_rot90_f): Add "_" or "_f" suffix.
> * config/arm/iterators.md (mve_insn): Add vcadd, vhcadd.
> (isu): Add UNSPEC_VCADD90, UNSPEC_VCADD270,
> VCADDQ_ROT270_M_U,
> VCADDQ_ROT270_M_S, VCADDQ_ROT90_M_U,
> VCADDQ_ROT90_M_S,
> VHCADDQ_ROT90_M_S, VHCADDQ_ROT270_M_S,
> VHCADDQ_ROT90_S,
> VHCADDQ_ROT270_S.
> (rot): Add VCADDQ_ROT90_M_F, VCADDQ_ROT90_M_S,
> VCADDQ_ROT90_M_U,
> VCADDQ_ROT270_M_F, VCADDQ_ROT270_M_S,
> VCADDQ_ROT270_M_U,
> VHCADDQ_ROT90_S, VHCADDQ_ROT270_S, VHCADDQ_ROT90_M_S,
> VHCADDQ_ROT270_M_S.
> (mve_rot): Add VCADDQ_ROT90_M_F, VCADDQ_ROT90_M_S,
> VCADDQ_ROT90_M_U, VCADDQ_ROT270_M_F,
> VCADDQ_ROT270_M_S,
> VCADDQ_ROT270_M_U, VHCADDQ_ROT90_S, VHCADDQ_ROT270_S,
> VHCADDQ_ROT90_M_S, VHCADDQ_ROT270_M_S.
> (supf): Add VHCADDQ_ROT90_M_S, VHCADDQ_ROT270_M_S,
> VHCADDQ_ROT90_S, VHCADDQ_ROT270_S, UNSPEC_VCADD90,
> UNSPEC_VCADD270.
> (VCADDQ_ROT270_M): Delete.
> (VCADDQ_M_F VxCADDQ VxCADDQ_M): New.
> (VCADDQ_ROT90_M): Delete.
> * config/arm/mve.md (mve_vcaddq<mve_rot><mode>)
> (mve_vhcaddq_rot270_s<mode>, mve_vhcaddq_rot90_s<mode>):
> Merge
> into ...
> (@mve_<mve_insn>q<mve_rot>_<supf><mode>): ... this.
> (mve_vcaddq<mve_rot><mode>): Rename into ...
> (@mve_<mve_insn>q<mve_rot>_f<mode>): ... this
> (mve_vcaddq_rot270_m_<supf><mode>)
> (mve_vcaddq_rot90_m_<supf><mode>,
> mve_vhcaddq_rot270_m_s<mode>)
> (mve_vhcaddq_rot90_m_s<mode>): Merge into ...
> (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): ... this.
> (mve_vcaddq_rot270_m_f<mode>, mve_vcaddq_rot90_m_f<mode>):
> Merge
> into ...
> (@mve_<mve_insn>q<mve_rot>_m_f<mode>): ... this.
> ---
> gcc/config/arm/arm_mve_builtins.def | 6 +-
> gcc/config/arm/iterators.md | 38 +++++++-
> gcc/config/arm/mve.md | 135 +++++-----------------------
> 3 files changed, 62 insertions(+), 117 deletions(-)
>
> diff --git a/gcc/config/arm/arm_mve_builtins.def
> b/gcc/config/arm/arm_mve_builtins.def
> index 8de765de3b0..63ad1845593 100644
> --- a/gcc/config/arm/arm_mve_builtins.def
> +++ b/gcc/config/arm/arm_mve_builtins.def
> @@ -187,6 +187,10 @@ VAR3 (BINOP_NONE_NONE_NONE, vmaxvq_s, v16qi,
> v8hi, v4si)
> VAR3 (BINOP_NONE_NONE_NONE, vmaxq_s, v16qi, v8hi, v4si)
> VAR3 (BINOP_NONE_NONE_NONE, vhsubq_s, v16qi, v8hi, v4si)
> VAR3 (BINOP_NONE_NONE_NONE, vhsubq_n_s, v16qi, v8hi, v4si)
> +VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot90_, v16qi, v8hi, v4si)
> +VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot270_, v16qi, v8hi, v4si)
> +VAR2 (BINOP_NONE_NONE_NONE, vcaddq_rot90_f, v8hf, v4sf)
> +VAR2 (BINOP_NONE_NONE_NONE, vcaddq_rot270_f, v8hf, v4sf)
> VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot90_s, v16qi, v8hi, v4si)
> VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si)
> VAR3 (BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si)
> @@ -870,8 +874,6 @@ VAR3
> (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_vec_u, v16qi,
> v8hi, v4si)
> VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_carry_u,
> v16qi, v8hi, v4si)
>
> /* optabs without any suffixes. */
> -VAR5 (BINOP_NONE_NONE_NONE, vcaddq_rot90, v16qi, v8hi, v4si, v8hf,
> v4sf)
> -VAR5 (BINOP_NONE_NONE_NONE, vcaddq_rot270, v16qi, v8hi, v4si, v8hf,
> v4sf)
> VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot90, v8hf, v4sf)
> VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot270, v8hf, v4sf)
> VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot180, v8hf, v4sf)
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index 9e77af55d60..da1ead34e58 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -902,6 +902,7 @@
> ])
>
> (define_int_attr mve_insn [
> + (UNSPEC_VCADD90 "vcadd") (UNSPEC_VCADD270 "vcadd")
> (VABAVQ_P_S "vabav") (VABAVQ_P_U "vabav")
> (VABAVQ_S "vabav") (VABAVQ_U "vabav")
> (VABDQ_M_S "vabd") (VABDQ_M_U "vabd") (VABDQ_M_F
> "vabd")
> @@ -925,6 +926,8 @@
> (VBICQ_N_S "vbic") (VBICQ_N_U "vbic")
> (VBRSRQ_M_N_S "vbrsr") (VBRSRQ_M_N_U "vbrsr")
> (VBRSRQ_M_N_F "vbrsr")
> (VBRSRQ_N_S "vbrsr") (VBRSRQ_N_U "vbrsr") (VBRSRQ_N_F
> "vbrsr")
> + (VCADDQ_ROT270_M_U "vcadd") (VCADDQ_ROT270_M_S
> "vcadd") (VCADDQ_ROT270_M_F "vcadd")
> + (VCADDQ_ROT90_M_U "vcadd") (VCADDQ_ROT90_M_S
> "vcadd") (VCADDQ_ROT90_M_F "vcadd")
> (VCLSQ_M_S "vcls")
> (VCLSQ_S "vcls")
> (VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz")
> @@ -944,6 +947,8 @@
> (VHADDQ_M_S "vhadd") (VHADDQ_M_U "vhadd")
> (VHADDQ_N_S "vhadd") (VHADDQ_N_U "vhadd")
> (VHADDQ_S "vhadd") (VHADDQ_U "vhadd")
> + (VHCADDQ_ROT90_M_S "vhcadd") (VHCADDQ_ROT270_M_S
> "vhcadd")
> + (VHCADDQ_ROT90_S "vhcadd") (VHCADDQ_ROT270_S
> "vhcadd")
> (VHSUBQ_M_N_S "vhsub") (VHSUBQ_M_N_U "vhsub")
> (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub")
> (VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub")
> @@ -1190,7 +1195,10 @@
> ])
>
> (define_int_attr isu [
> + (UNSPEC_VCADD90 "i") (UNSPEC_VCADD270 "i")
> (VABSQ_M_S "s")
> + (VCADDQ_ROT270_M_U "i") (VCADDQ_ROT270_M_S "i")
> + (VCADDQ_ROT90_M_U "i") (VCADDQ_ROT90_M_S "i")
> (VCLSQ_M_S "s")
> (VCLZQ_M_S "i")
> (VCLZQ_M_U "i")
> @@ -1214,6 +1222,8 @@
> (VCMPNEQ_M_N_U "i")
> (VCMPNEQ_M_S "i")
> (VCMPNEQ_M_U "i")
> + (VHCADDQ_ROT90_M_S "s") (VHCADDQ_ROT270_M_S "s")
> + (VHCADDQ_ROT90_S "s") (VHCADDQ_ROT270_S "s")
> (VMOVNBQ_M_S "i") (VMOVNBQ_M_U "i")
> (VMOVNBQ_S "i") (VMOVNBQ_U "i")
> (VMOVNTQ_M_S "i") (VMOVNTQ_M_U "i")
> @@ -2155,6 +2165,16 @@
>
> (define_int_attr rot [(UNSPEC_VCADD90 "90")
> (UNSPEC_VCADD270 "270")
> + (VCADDQ_ROT90_M_F "90")
> + (VCADDQ_ROT90_M_S "90")
> + (VCADDQ_ROT90_M_U "90")
> + (VCADDQ_ROT270_M_F "270")
> + (VCADDQ_ROT270_M_S "270")
> + (VCADDQ_ROT270_M_U "270")
> + (VHCADDQ_ROT90_S "90")
> + (VHCADDQ_ROT270_S "270")
> + (VHCADDQ_ROT90_M_S "90")
> + (VHCADDQ_ROT270_M_S "270")
> (UNSPEC_VCMUL "0")
> (UNSPEC_VCMUL90 "90")
> (UNSPEC_VCMUL180 "180")
> @@ -2193,6 +2213,16 @@
>
> (define_int_attr mve_rot [(UNSPEC_VCADD90 "_rot90")
> (UNSPEC_VCADD270 "_rot270")
> + (VCADDQ_ROT90_M_F "_rot90")
> + (VCADDQ_ROT90_M_S "_rot90")
> + (VCADDQ_ROT90_M_U "_rot90")
> + (VCADDQ_ROT270_M_F "_rot270")
> + (VCADDQ_ROT270_M_S "_rot270")
> + (VCADDQ_ROT270_M_U "_rot270")
> + (VHCADDQ_ROT90_S "_rot90")
> + (VHCADDQ_ROT270_S "_rot270")
> + (VHCADDQ_ROT90_M_S "_rot90")
> + (VHCADDQ_ROT270_M_S "_rot270")
> (UNSPEC_VCMLA "")
> (UNSPEC_VCMLA90 "_rot90")
> (UNSPEC_VCMLA180 "_rot180")
> @@ -2535,6 +2565,9 @@
> (VRMLALDAVHAQ_P_S "s") (VRMLALDAVHAQ_P_U "u")
> (VQSHLUQ_M_N_S "s")
> (VQSHLUQ_N_S "s")
> + (VHCADDQ_ROT90_M_S "s") (VHCADDQ_ROT270_M_S
> "s")
> + (VHCADDQ_ROT90_S "s") (VHCADDQ_ROT270_S "s")
> + (UNSPEC_VCADD90 "") (UNSPEC_VCADD270 "")
> ])
>
> ;; Both kinds of return insn.
> @@ -2767,7 +2800,9 @@
> (define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S])
> (define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S])
> (define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
> -(define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U
> VCADDQ_ROT270_M_S])
> +(define_int_iterator VCADDQ_M_F [VCADDQ_ROT90_M_F
> VCADDQ_ROT270_M_F])
> +(define_int_iterator VxCADDQ [UNSPEC_VCADD90 UNSPEC_VCADD270
> VHCADDQ_ROT90_S VHCADDQ_ROT270_S])
> +(define_int_iterator VxCADDQ_M [VHCADDQ_ROT90_M_S
> VHCADDQ_ROT270_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S
> VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
> (define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
> (define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
> (define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
> @@ -2777,7 +2812,6 @@
> (define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
> (define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
> (define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
> -(define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U
> VCADDQ_ROT90_M_S])
> (define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S
> VMULLTQ_INT_M_U])
> (define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
> (define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 74909ce47e1..a6db6d1b81d 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -839,17 +839,20 @@
> ])
>
> ;;
> -;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270])
> +;; [vcaddq_rot90_s, vcadd_rot90_u]
> +;; [vcaddq_rot270_s, vcadd_rot270_u]
> +;; [vhcaddq_rot90_s]
> +;; [vhcaddq_rot270_s]
> ;;
> -(define_insn "mve_vcaddq<mve_rot><mode>"
> +(define_insn "@mve_<mve_insn>q<mve_rot>_<supf><mode>"
> [
> (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
> (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand"
> "w")
> (match_operand:MVE_2 2 "s_register_operand" "w")]
> - VCADD))
> + VxCADDQ))
> ]
> "TARGET_HAVE_MVE"
> - "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #<rot>"
> + "<mve_insn>.<isu>%#<V_sz_elem>\t%q0, %q1, %q2, #<rot>"
> [(set_attr "type" "mve_move")
> ])
>
> @@ -904,36 +907,6 @@
> [(set_attr "type" "mve_move")
> ])
>
> -;;
> -;; [vhcaddq_rot270_s])
> -;;
> -(define_insn "mve_vhcaddq_rot270_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand"
> "w")
> - (match_operand:MVE_2 2 "s_register_operand" "w")]
> - VHCADDQ_ROT270_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270"
> - [(set_attr "type" "mve_move")
> -])
> -
> -;;
> -;; [vhcaddq_rot90_s])
> -;;
> -(define_insn "mve_vhcaddq_rot90_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand"
> "w")
> - (match_operand:MVE_2 2 "s_register_operand" "w")]
> - VHCADDQ_ROT90_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90"
> - [(set_attr "type" "mve_move")
> -])
> -
> ;;
> ;; [vmaxaq_s]
> ;; [vminaq_s]
> @@ -1238,9 +1211,9 @@
> ])
>
> ;;
> -;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270])
> +;; [vcaddq_rot90_f, vcaddq_rot270_f]
> ;;
> -(define_insn "mve_vcaddq<mve_rot><mode>"
> +(define_insn "@mve_<mve_insn>q<mve_rot>_f<mode>"
> [
> (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
> (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand"
> "w")
> @@ -1248,7 +1221,7 @@
> VCADD))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> - "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #<rot>"
> + "<mve_insn>.f%#<V_sz_elem>\t%q0, %q1, %q2, #<rot>"
> [(set_attr "type" "mve_move")
> ])
>
> @@ -2788,36 +2761,22 @@
> (set_attr "length""8")])
>
> ;;
> -;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s])
> +;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s]
> +;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s]
> +;; [vhcaddq_rot90_m_s]
> +;; [vhcaddq_rot270_m_s]
> ;;
> -(define_insn "mve_vcaddq_rot270_m_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q<mve_rot>_m_<supf><mode>"
> [
> (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
> (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> (match_operand:MVE_2 2 "s_register_operand" "w")
> (match_operand:MVE_2 3 "s_register_operand" "w")
> (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VCADDQ_ROT270_M))
> + VxCADDQ_M))
> ]
> "TARGET_HAVE_MVE"
> - "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s])
> -;;
> -(define_insn "mve_vcaddq_rot90_m_<supf><mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VCADDQ_ROT90_M))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90"
> + "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2, %q3, #<rot>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> @@ -2974,40 +2933,6 @@
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> -;;
> -;; [vhcaddq_rot270_m_s])
> -;;
> -(define_insn "mve_vhcaddq_rot270_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VHCADDQ_ROT270_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vhcaddq_rot90_m_s])
> -;;
> -(define_insn "mve_vhcaddq_rot90_m_s<mode>"
> - [
> - (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
> - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> - (match_operand:MVE_2 2 "s_register_operand" "w")
> - (match_operand:MVE_2 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VHCADDQ_ROT90_M_S))
> - ]
> - "TARGET_HAVE_MVE"
> - "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> ;;
> ;; [vmlaldavaq_p_u, vmlaldavaq_p_s]
> ;; [vmlaldavaxq_p_s]
> @@ -3247,36 +3172,20 @@
> (set_attr "length""8")])
>
> ;;
> -;; [vcaddq_rot270_m_f])
> -;;
> -(define_insn "mve_vcaddq_rot270_m_f<mode>"
> - [
> - (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
> - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
> - (match_operand:MVE_0 2 "s_register_operand" "w")
> - (match_operand:MVE_0 3 "s_register_operand" "w")
> - (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VCADDQ_ROT270_M_F))
> - ]
> - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> - "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #270"
> - [(set_attr "type" "mve_move")
> - (set_attr "length""8")])
> -
> -;;
> -;; [vcaddq_rot90_m_f])
> +;; [vcaddq_rot90_m_f]
> +;; [vcaddq_rot270_m_f]
> ;;
> -(define_insn "mve_vcaddq_rot90_m_f<mode>"
> +(define_insn "@mve_<mve_insn>q<mve_rot>_m_f<mode>"
> [
> (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
> (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
> (match_operand:MVE_0 2 "s_register_operand" "w")
> (match_operand:MVE_0 3 "s_register_operand" "w")
> (match_operand:<MVE_VPRED> 4
> "vpr_register_operand" "Up")]
> - VCADDQ_ROT90_M_F))
> + VCADDQ_M_F))
> ]
> "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
> - "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #90"
> + "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%q0, %q2, %q3, #<rot>"
> [(set_attr "type" "mve_move")
> (set_attr "length""8")])
>
> --
> 2.34.1
@@ -187,6 +187,10 @@ VAR3 (BINOP_NONE_NONE_NONE, vmaxvq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vmaxq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vhsubq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vhsubq_n_s, v16qi, v8hi, v4si)
+VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot90_, v16qi, v8hi, v4si)
+VAR3 (BINOP_NONE_NONE_NONE, vcaddq_rot270_, v16qi, v8hi, v4si)
+VAR2 (BINOP_NONE_NONE_NONE, vcaddq_rot90_f, v8hf, v4sf)
+VAR2 (BINOP_NONE_NONE_NONE, vcaddq_rot270_f, v8hf, v4sf)
VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot90_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vhcaddq_rot270_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vhaddq_s, v16qi, v8hi, v4si)
@@ -870,8 +874,6 @@ VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_vec_u, v16qi, v8hi, v4si)
VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_PRED, vshlcq_m_carry_u, v16qi, v8hi, v4si)
/* optabs without any suffixes. */
-VAR5 (BINOP_NONE_NONE_NONE, vcaddq_rot90, v16qi, v8hi, v4si, v8hf, v4sf)
-VAR5 (BINOP_NONE_NONE_NONE, vcaddq_rot270, v16qi, v8hi, v4si, v8hf, v4sf)
VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot90, v8hf, v4sf)
VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot270, v8hf, v4sf)
VAR2 (BINOP_NONE_NONE_NONE, vcmulq_rot180, v8hf, v4sf)
@@ -902,6 +902,7 @@
])
(define_int_attr mve_insn [
+ (UNSPEC_VCADD90 "vcadd") (UNSPEC_VCADD270 "vcadd")
(VABAVQ_P_S "vabav") (VABAVQ_P_U "vabav")
(VABAVQ_S "vabav") (VABAVQ_U "vabav")
(VABDQ_M_S "vabd") (VABDQ_M_U "vabd") (VABDQ_M_F "vabd")
@@ -925,6 +926,8 @@
(VBICQ_N_S "vbic") (VBICQ_N_U "vbic")
(VBRSRQ_M_N_S "vbrsr") (VBRSRQ_M_N_U "vbrsr") (VBRSRQ_M_N_F "vbrsr")
(VBRSRQ_N_S "vbrsr") (VBRSRQ_N_U "vbrsr") (VBRSRQ_N_F "vbrsr")
+ (VCADDQ_ROT270_M_U "vcadd") (VCADDQ_ROT270_M_S "vcadd") (VCADDQ_ROT270_M_F "vcadd")
+ (VCADDQ_ROT90_M_U "vcadd") (VCADDQ_ROT90_M_S "vcadd") (VCADDQ_ROT90_M_F "vcadd")
(VCLSQ_M_S "vcls")
(VCLSQ_S "vcls")
(VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz")
@@ -944,6 +947,8 @@
(VHADDQ_M_S "vhadd") (VHADDQ_M_U "vhadd")
(VHADDQ_N_S "vhadd") (VHADDQ_N_U "vhadd")
(VHADDQ_S "vhadd") (VHADDQ_U "vhadd")
+ (VHCADDQ_ROT90_M_S "vhcadd") (VHCADDQ_ROT270_M_S "vhcadd")
+ (VHCADDQ_ROT90_S "vhcadd") (VHCADDQ_ROT270_S "vhcadd")
(VHSUBQ_M_N_S "vhsub") (VHSUBQ_M_N_U "vhsub")
(VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub")
(VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub")
@@ -1190,7 +1195,10 @@
])
(define_int_attr isu [
+ (UNSPEC_VCADD90 "i") (UNSPEC_VCADD270 "i")
(VABSQ_M_S "s")
+ (VCADDQ_ROT270_M_U "i") (VCADDQ_ROT270_M_S "i")
+ (VCADDQ_ROT90_M_U "i") (VCADDQ_ROT90_M_S "i")
(VCLSQ_M_S "s")
(VCLZQ_M_S "i")
(VCLZQ_M_U "i")
@@ -1214,6 +1222,8 @@
(VCMPNEQ_M_N_U "i")
(VCMPNEQ_M_S "i")
(VCMPNEQ_M_U "i")
+ (VHCADDQ_ROT90_M_S "s") (VHCADDQ_ROT270_M_S "s")
+ (VHCADDQ_ROT90_S "s") (VHCADDQ_ROT270_S "s")
(VMOVNBQ_M_S "i") (VMOVNBQ_M_U "i")
(VMOVNBQ_S "i") (VMOVNBQ_U "i")
(VMOVNTQ_M_S "i") (VMOVNTQ_M_U "i")
@@ -2155,6 +2165,16 @@
(define_int_attr rot [(UNSPEC_VCADD90 "90")
(UNSPEC_VCADD270 "270")
+ (VCADDQ_ROT90_M_F "90")
+ (VCADDQ_ROT90_M_S "90")
+ (VCADDQ_ROT90_M_U "90")
+ (VCADDQ_ROT270_M_F "270")
+ (VCADDQ_ROT270_M_S "270")
+ (VCADDQ_ROT270_M_U "270")
+ (VHCADDQ_ROT90_S "90")
+ (VHCADDQ_ROT270_S "270")
+ (VHCADDQ_ROT90_M_S "90")
+ (VHCADDQ_ROT270_M_S "270")
(UNSPEC_VCMUL "0")
(UNSPEC_VCMUL90 "90")
(UNSPEC_VCMUL180 "180")
@@ -2193,6 +2213,16 @@
(define_int_attr mve_rot [(UNSPEC_VCADD90 "_rot90")
(UNSPEC_VCADD270 "_rot270")
+ (VCADDQ_ROT90_M_F "_rot90")
+ (VCADDQ_ROT90_M_S "_rot90")
+ (VCADDQ_ROT90_M_U "_rot90")
+ (VCADDQ_ROT270_M_F "_rot270")
+ (VCADDQ_ROT270_M_S "_rot270")
+ (VCADDQ_ROT270_M_U "_rot270")
+ (VHCADDQ_ROT90_S "_rot90")
+ (VHCADDQ_ROT270_S "_rot270")
+ (VHCADDQ_ROT90_M_S "_rot90")
+ (VHCADDQ_ROT270_M_S "_rot270")
(UNSPEC_VCMLA "")
(UNSPEC_VCMLA90 "_rot90")
(UNSPEC_VCMLA180 "_rot180")
@@ -2535,6 +2565,9 @@
(VRMLALDAVHAQ_P_S "s") (VRMLALDAVHAQ_P_U "u")
(VQSHLUQ_M_N_S "s")
(VQSHLUQ_N_S "s")
+ (VHCADDQ_ROT90_M_S "s") (VHCADDQ_ROT270_M_S "s")
+ (VHCADDQ_ROT90_S "s") (VHCADDQ_ROT270_S "s")
+ (UNSPEC_VCADD90 "") (UNSPEC_VCADD270 "")
])
;; Both kinds of return insn.
@@ -2767,7 +2800,9 @@
(define_int_iterator VANDQ_M [VANDQ_M_U VANDQ_M_S])
(define_int_iterator VBICQ_M [VBICQ_M_U VBICQ_M_S])
(define_int_iterator VSHLQ_M_N [VSHLQ_M_N_S VSHLQ_M_N_U])
-(define_int_iterator VCADDQ_ROT270_M [VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
+(define_int_iterator VCADDQ_M_F [VCADDQ_ROT90_M_F VCADDQ_ROT270_M_F])
+(define_int_iterator VxCADDQ [UNSPEC_VCADD90 UNSPEC_VCADD270 VHCADDQ_ROT90_S VHCADDQ_ROT270_S])
+(define_int_iterator VxCADDQ_M [VHCADDQ_ROT90_M_S VHCADDQ_ROT270_M_S VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S VCADDQ_ROT270_M_U VCADDQ_ROT270_M_S])
(define_int_iterator VQRSHLQ_M [VQRSHLQ_M_U VQRSHLQ_M_S])
(define_int_iterator VQADDQ_M_N [VQADDQ_M_N_U VQADDQ_M_N_S])
(define_int_iterator VADDQ_M_N [VADDQ_M_N_S VADDQ_M_N_U])
@@ -2777,7 +2812,6 @@
(define_int_iterator VMLADAVAQ_P [VMLADAVAQ_P_U VMLADAVAQ_P_S])
(define_int_iterator VBRSRQ_M_N [VBRSRQ_M_N_U VBRSRQ_M_N_S])
(define_int_iterator VMULQ_M_N [VMULQ_M_N_U VMULQ_M_N_S])
-(define_int_iterator VCADDQ_ROT90_M [VCADDQ_ROT90_M_U VCADDQ_ROT90_M_S])
(define_int_iterator VMULLTQ_INT_M [VMULLTQ_INT_M_S VMULLTQ_INT_M_U])
(define_int_iterator VEORQ_M [VEORQ_M_S VEORQ_M_U])
(define_int_iterator VSHRQ_M_N [VSHRQ_M_N_S VSHRQ_M_N_U])
@@ -839,17 +839,20 @@
])
;;
-;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270])
+;; [vcaddq_rot90_s, vcadd_rot90_u]
+;; [vcaddq_rot270_s, vcadd_rot270_u]
+;; [vhcaddq_rot90_s]
+;; [vhcaddq_rot270_s]
;;
-(define_insn "mve_vcaddq<mve_rot><mode>"
+(define_insn "@mve_<mve_insn>q<mve_rot>_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
- VCADD))
+ VxCADDQ))
]
"TARGET_HAVE_MVE"
- "vcadd.i%#<V_sz_elem> %q0, %q1, %q2, #<rot>"
+ "<mve_insn>.<isu>%#<V_sz_elem>\t%q0, %q1, %q2, #<rot>"
[(set_attr "type" "mve_move")
])
@@ -904,36 +907,6 @@
[(set_attr "type" "mve_move")
])
-;;
-;; [vhcaddq_rot270_s])
-;;
-(define_insn "mve_vhcaddq_rot270_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VHCADDQ_ROT270_S))
- ]
- "TARGET_HAVE_MVE"
- "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #270"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vhcaddq_rot90_s])
-;;
-(define_insn "mve_vhcaddq_rot90_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VHCADDQ_ROT90_S))
- ]
- "TARGET_HAVE_MVE"
- "vhcadd.s%#<V_sz_elem>\t%q0, %q1, %q2, #90"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vmaxaq_s]
;; [vminaq_s]
@@ -1238,9 +1211,9 @@
])
;;
-;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270])
+;; [vcaddq_rot90_f, vcaddq_rot270_f]
;;
-(define_insn "mve_vcaddq<mve_rot><mode>"
+(define_insn "@mve_<mve_insn>q<mve_rot>_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
@@ -1248,7 +1221,7 @@
VCADD))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vcadd.f%#<V_sz_elem> %q0, %q1, %q2, #<rot>"
+ "<mve_insn>.f%#<V_sz_elem>\t%q0, %q1, %q2, #<rot>"
[(set_attr "type" "mve_move")
])
@@ -2788,36 +2761,22 @@
(set_attr "length""8")])
;;
-;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s])
+;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s]
+;; [vcaddq_rot270_m_u, vcaddq_rot270_m_s]
+;; [vhcaddq_rot90_m_s]
+;; [vhcaddq_rot270_m_s]
;;
-(define_insn "mve_vcaddq_rot270_m_<supf><mode>"
+(define_insn "@mve_<mve_insn>q<mve_rot>_m_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:MVE_2 3 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VCADDQ_ROT270_M))
+ VxCADDQ_M))
]
"TARGET_HAVE_MVE"
- "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #270"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vcaddq_rot90_m_u, vcaddq_rot90_m_s])
-;;
-(define_insn "mve_vcaddq_rot90_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VCADDQ_ROT90_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vcaddt.i%#<V_sz_elem> %q0, %q2, %q3, #90"
+ "vpst\;<mve_insn>t.<isu>%#<V_sz_elem>\t%q0, %q2, %q3, #<rot>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -2974,40 +2933,6 @@
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vhcaddq_rot270_m_s])
-;;
-(define_insn "mve_vhcaddq_rot270_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VHCADDQ_ROT270_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #270"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vhcaddq_rot90_m_s])
-;;
-(define_insn "mve_vhcaddq_rot90_m_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VHCADDQ_ROT90_M_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vhcaddt.s%#<V_sz_elem>\t%q0, %q2, %q3, #90"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vmlaldavaq_p_u, vmlaldavaq_p_s]
;; [vmlaldavaxq_p_s]
@@ -3247,36 +3172,20 @@
(set_attr "length""8")])
;;
-;; [vcaddq_rot270_m_f])
-;;
-(define_insn "mve_vcaddq_rot270_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VCADDQ_ROT270_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #270"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vcaddq_rot90_m_f])
+;; [vcaddq_rot90_m_f]
+;; [vcaddq_rot270_m_f]
;;
-(define_insn "mve_vcaddq_rot90_m_f<mode>"
+(define_insn "@mve_<mve_insn>q<mve_rot>_m_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "<earlyclobber_32>")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:MVE_0 2 "s_register_operand" "w")
(match_operand:MVE_0 3 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VCADDQ_ROT90_M_F))
+ VCADDQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vcaddt.f%#<V_sz_elem> %q0, %q2, %q3, #90"
+ "vpst\;<mve_insn>t.f%#<V_sz_elem>\t%q0, %q2, %q3, #<rot>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])