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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id z25-20020a170906271900b00986f786c94asi6178207ejc.113.2023.07.12.22.10.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 22:10:59 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=R3dIye5W; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E24283857735 for ; Thu, 13 Jul 2023 05:10:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E24283857735 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689225055; bh=HFnZMNvnIYFByggKzH8QR/R2fNSckdQ/9Wl/dsw7JCQ=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=R3dIye5WScEKsgqQTf4zAkxvBaO713mTdkt/5UPj85W2a+hkTsT+NpMlx1KyuyRzG oPA+rdYXpwC8yQOhA1kUTWONgXNUvSvci7/VFCejUDk8IRP3yzAy9TqXVX28NSaQ9V x25x3mFAMqG67sDZ7kKoy7pfBi+uZhAX0N2J1U84= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 7D8473858C41 for ; Thu, 13 Jul 2023 05:10:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7D8473858C41 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="431239294" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="431239294" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 22:10:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="791893797" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="791893797" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 12 Jul 2023 22:10:03 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 088A61005695; Thu, 13 Jul 2023 13:10:03 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v2] RISC-V: Add more tests for RVV floating-point FRM. Date: Thu, 13 Jul 2023 13:10:01 +0800 Message-Id: <20230713051001.2869210-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230712150302.3517511-1-pan2.li@intel.com> References: <20230712150302.3517511-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771227830681762854 X-GMAIL-MSGID: 1771280856028707678 From: Pan Li Add more test cases include both the asm check and run for RVV FRM. Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-8.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-insert-9.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-1.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-2.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-3.c: New test. Signed-off-by: Pan Li > --- .../rvv/base/float-point-frm-insert-10.c | 23 ++++++ .../riscv/rvv/base/float-point-frm-insert-7.c | 29 +++++++ .../riscv/rvv/base/float-point-frm-insert-8.c | 27 +++++++ .../riscv/rvv/base/float-point-frm-insert-9.c | 24 ++++++ .../riscv/rvv/base/float-point-frm-run-1.c | 79 +++++++++++++++++++ .../riscv/rvv/base/float-point-frm-run-2.c | 70 ++++++++++++++++ .../riscv/rvv/base/float-point-frm-run-3.c | 71 +++++++++++++++++ 7 files changed, 323 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c new file mode 100644 index 00000000000..c46910b878c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + asm volatile ( + "addi %0, %0, 0x12" + :"+r"(vl) + : + : + ); + + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c new file mode 100644 index 00000000000..7b1602fd509 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +normalize_vl (size_t vl) +{ + if (vl % 4 == 0) + return vl; + + return ((vl / 4) + 1) * 4; +} + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + + vl = normalize_vl (vl); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c new file mode 100644 index 00000000000..37481ddac38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +size_t __attribute__ ((noinline)) +normalize_vl (size_t vl) +{ + if (vl % 4 == 0) + return vl; + + return ((vl / 4) + 1) * 4; +} + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + vl = normalize_vl (vl); + + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c new file mode 100644 index 00000000000..7ae834ad531 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +void +test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) +{ + vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl); + + asm volatile ( + "fsrmi 4" + : + : + :"frm" + ); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + *(vfloat32m1_t *)out = result; +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c new file mode 100644 index 00000000000..210c49c5e8d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c @@ -0,0 +1,79 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O3 -Wno-psabi" } */ + +#include "riscv_vector.h" +#include +#include + +static int +get_frm () +{ + int frm = -1; + + __asm__ volatile ( + "frrm %0" + :"=r"(frm) + : + : + ); + + return frm; +} + +static void +set_frm (int frm) +{ + __asm__ volatile ( + "fsrm %0" + : + :"r"(frm) + : + ); +} + +static inline void +assert_equal (int a, int b, char *message) +{ + if (a != b) + { + printf (message); + __builtin_abort (); + } +} + +vfloat32m1_t __attribute__ ((noinline)) +test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) +{ + set_frm (0); + + vfloat32m1_t result; + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl); + assert_equal (1, get_frm (), "The value of frm register should be 1."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl); + assert_equal (2, get_frm (), "The value of frm register should be 2."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl); + assert_equal (3, get_frm (), "The value of frm register should be 3."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl); + assert_equal (0, get_frm (), "The value of frm register should be 0."); + + return result; +} + +int +main () +{ + size_t vl = 8; + vfloat32m1_t op1; + vfloat32m1_t op2; + + test_float_point_frm_run (op1, op2, vl); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c new file mode 100644 index 00000000000..a7036529cf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c @@ -0,0 +1,70 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O3 -Wno-psabi" } */ + +#include "riscv_vector.h" +#include +#include + +static int +get_frm () +{ + int frm = -1; + + __asm__ volatile ( + "frrm %0" + :"=r"(frm) + : + : + ); + + return frm; +} + +static void +set_frm (int frm) +{ + __asm__ volatile ( + "fsrm %0" + : + :"r"(frm) + : + ); +} + +static inline void +assert_equal (int a, int b, char *message) +{ + if (a != b) + { + fprintf (stdout, "%s, but get %d != %d\n", message, a, b); + __builtin_abort (); + } +} + +vfloat32m1_t __attribute__ ((noinline)) +test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) +{ + set_frm (0); + + vfloat32m1_t result = {}; + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl); + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl); + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); + + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + return result; +} + +int +main () +{ + size_t vl = 8; + vfloat32m1_t op1 = {}; + vfloat32m1_t op2 = {}; + + test_float_point_frm_run (op1, op2, vl); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c new file mode 100644 index 00000000000..6924bdf6a05 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c @@ -0,0 +1,71 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O3 -Wno-psabi" } */ + +#include "riscv_vector.h" +#include +#include + +static int +get_frm () +{ + int frm = -1; + + __asm__ volatile ( + "frrm %0" + :"=r"(frm) + : + : + ); + + return frm; +} + +static void +set_frm (int frm) +{ + __asm__ volatile ( + "fsrm %0" + : + :"r"(frm) + : + ); +} + +static inline void +assert_equal (int a, int b, char *message) +{ + if (a != b) + { + fprintf (stdout, "%s, but get %d != %d\n", message, a, b); + __builtin_abort (); + } +} + +vfloat32m1_t __attribute__ ((noinline)) +test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) +{ + set_frm (0); + + vfloat32m1_t result = {}; + + result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl); + + result = __riscv_vfadd_vv_f32m1 (op1, result, vl); + result = __riscv_vfadd_vv_f32m1 (op1, result, vl); + + assert_equal (4, get_frm (), "The value of frm register should be 4."); + + return result; +} + +int +main () +{ + size_t vl = 8; + vfloat32m1_t op1 = {}; + vfloat32m1_t op2 = {}; + + test_float_point_frm_run (op1, op2, vl); + + return 0; +}