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[8.43.85.97]) by mx.google.com with ESMTPS id y6-20020a056402134600b0051e19396481si6281210edw.11.2023.07.12.22.04.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jul 2023 22:04:42 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=CEW0UB1I; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 99C65385700F for ; Thu, 13 Jul 2023 05:04:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 99C65385700F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689224654; bh=DMtYfg9rdmBZQHHidrKGYWK/WXxa+icd/1D8hG42Vqs=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=CEW0UB1IrfOEbpI63dEcRgN8NwtnarXzDZ2XXIKoKyZCP3B4svid9KrzQNBgoB5UY Ig7uVKWDKUA5O/itOA2peftZ4woZQWmDOeW5mi4WYDnaj2AGyfrpupv4jcTHQHC9QP gSI078YJGCqlYomMXZS/+sO3cR/txzeDS+8jWJYg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 650853857023 for ; Thu, 13 Jul 2023 05:02:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 650853857023 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="362551440" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="362551440" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 22:02:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="699115430" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="699115430" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga006.jf.intel.com with ESMTP; 12 Jul 2023 22:02:37 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id D72D91005695; Thu, 13 Jul 2023 13:02:36 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v3] RISC-V: Refactor riscv mode after for VXRM and FRM Date: Thu, 13 Jul 2023 13:02:35 +0800 Message-Id: <20230713050235.2864130-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230712054609.3958442-1-pan2.li@intel.com> References: <20230712054609.3958442-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771192525704265527 X-GMAIL-MSGID: 1771280460136592950 From: Pan Li When investigate the FRM dynmaic rounding mode, we find the global unknown status is quite different between the fixed-point and floating-point. Thus, we separate the unknown function with extracting some inner common functions. We will also prepare more test cases in another PATCH. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv.cc (vxrm_rtx): New static var. (frm_rtx): Ditto. (global_state_unknown_p): Removed. (riscv_entity_mode_after): Removed. (asm_insn_p): New function. (vxrm_unknown_p): New function for fixed-point. (riscv_vxrm_mode_after): Ditto. (frm_unknown_dynamic_p): New function for floating-point. (riscv_frm_mode_after): Ditto. (riscv_mode_after): Leverage new functions. --- gcc/config/riscv/riscv.cc | 85 ++++++++++++++++++++++++++++----------- 1 file changed, 62 insertions(+), 23 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 706c18416db..6ed735d6983 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7701,17 +7701,24 @@ riscv_mode_needed (int entity, rtx_insn *insn) } } -/* Return true if the VXRM/FRM status of the INSN is unknown. */ +/* Return TRUE that an insn is asm. */ + static bool -global_state_unknown_p (rtx_insn *insn, unsigned int regno) +asm_insn_p (rtx_insn *insn) { - struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); - df_ref ref; + extract_insn (insn); + + return recog_data.is_asm; +} + +/* Return TRUE that an insn is unknown for VXRM. */ +static bool +vxrm_unknown_p (rtx_insn *insn) +{ /* Return true if there is a definition of VXRM. */ - for (ref = DF_INSN_INFO_DEFS (insn_info); ref; ref = DF_REF_NEXT_LOC (ref)) - if (DF_REF_REGNO (ref) == regno) - return true; + if (reg_set_p (gen_rtx_REG (SImode, VXRM_REGNUM), insn)) + return true; /* A CALL function may contain an instruction that modifies the VXRM, return true in this situation. */ @@ -7720,25 +7727,61 @@ global_state_unknown_p (rtx_insn *insn, unsigned int regno) /* Return true for all assembly since users may hardcode a assembly like this: asm volatile ("csrwi vxrm, 0"). */ - extract_insn (insn); - if (recog_data.is_asm) + if (asm_insn_p (insn)) + return true; + + return false; +} + +/* Return TRUE that an insn is unknown dynamic for FRM. */ + +static bool +frm_unknown_dynamic_p (rtx_insn *insn) +{ + /* Return true if there is a definition of FRM. */ + if (reg_set_p (gen_rtx_REG (SImode, FRM_REGNUM), insn)) return true; + + /* A CALL function may contain an instruction that modifies the FRM, + return true in this situation. */ + if (CALL_P (insn)) + return true; + return false; } +/* Return the mode that an insn results in for VXRM. */ + static int -riscv_entity_mode_after (int regnum, rtx_insn *insn, int mode, - int (*get_attr_mode) (rtx_insn *), int default_mode) +riscv_vxrm_mode_after (rtx_insn *insn, int mode) { - if (global_state_unknown_p (insn, regnum)) - return default_mode; - else if (recog_memoized (insn) < 0) + if (vxrm_unknown_p (insn)) + return VXRM_MODE_NONE; + + if (recog_memoized (insn) < 0) + return mode; + + if (reg_mentioned_p (gen_rtx_REG (SImode, VXRM_REGNUM), PATTERN (insn))) + return get_attr_vxrm_mode (insn); + else return mode; +} + +/* Return the mode that an insn results in for FRM. */ - rtx reg = gen_rtx_REG (SImode, regnum); - bool mentioned_p = reg_mentioned_p (reg, PATTERN (insn)); +static int +riscv_frm_mode_after (rtx_insn *insn, int mode) +{ + if (frm_unknown_dynamic_p (insn)) + return FRM_MODE_DYN; - return mentioned_p ? get_attr_mode (insn): mode; + if (recog_memoized (insn) < 0) + return mode; + + if (reg_mentioned_p (gen_rtx_REG (SImode, FRM_REGNUM), PATTERN (insn))) + return get_attr_frm_mode (insn); + else + return mode; } /* Return the mode that an insn results in. */ @@ -7749,13 +7792,9 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn) switch (entity) { case RISCV_VXRM: - return riscv_entity_mode_after (VXRM_REGNUM, insn, mode, - (int (*)(rtx_insn *)) get_attr_vxrm_mode, - VXRM_MODE_NONE); + return riscv_vxrm_mode_after (insn, mode); case RISCV_FRM: - return riscv_entity_mode_after (FRM_REGNUM, insn, mode, - (int (*)(rtx_insn *)) get_attr_frm_mode, - FRM_MODE_DYN); + return riscv_frm_mode_after (insn, mode); default: gcc_unreachable (); }