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[8.43.85.97]) by mx.google.com with ESMTPS id p10-20020a1709066a8a00b00992fd14244fsi1064348ejr.628.2023.07.10.20.40.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 20:40:39 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=mghJIS28; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 910A53857719 for ; Tue, 11 Jul 2023 03:40:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 910A53857719 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689046838; bh=F+4x9vVndKsZQgILlI6ZXx1BnRojChQEbLvxNTamXGU=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=mghJIS28UH5+TG9BwoVy3RPXiKJraow94cLlk0LmicTW62ZAugrXOCJQLmg5GvS9d 7rpufDtJ3InaS3zc+JkfCLazbzlhd5xGcCVuy7SZiyxJx9rI18YNOhOi2m/jdrg4qT fjibv3bU5rPT7bSq85dWZRI4gSYI4O8wR5OtQsGk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 1EC263858C5E for ; Tue, 11 Jul 2023 03:39:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1EC263858C5E X-IronPort-AV: E=McAfee;i="6600,9927,10767"; a="430601267" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="430601267" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2023 20:38:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10767"; a="786449827" X-IronPort-AV: E=Sophos;i="6.01,195,1684825200"; d="scan'208";a="786449827" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga008.fm.intel.com with ESMTP; 10 Jul 2023 20:38:40 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id F20241007800; Tue, 11 Jul 2023 11:38:39 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] i386: Guard 128 bit VAES builtins with AVX512VL Date: Tue, 11 Jul 2023 11:36:39 +0800 Message-Id: <20230711033639.3081376-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1771093978904889236 X-GMAIL-MSGID: 1771093978904889236 Hi all, Currently on trunk, both usage of intrin and builtin for 128 bit VAES ISA will result in ICE since we did not check AVX512VL until pattern, which is not user expected. This patch aims to fix that ICE and throw an error under this scenario. Regtested on x86-64-linux-gnu{-m32,}. Ok for trunk? BRs, Haochen Since commit 24a8acc, 128 bit intrin is enabled for VAES. However, AVX512VL is not checked until we reached into pattern, which reports an ICE. Added an AVX512VL guard at builtin to report error when checking ISA flags. gcc/ChangeLog: * config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins): Add OPTION_MASK_ISA_AVX512VL. * config/i386/i386-expand.cc (ix86_check_builtin_isa_match): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512vl-vaes-1.c: New test. --- gcc/config/i386/i386-builtins.cc | 12 ++++++++---- gcc/config/i386/i386-expand.cc | 4 +++- gcc/testsuite/gcc.target/i386/avx512vl-vaes-1.c | 12 ++++++++++++ 3 files changed, 23 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vaes-1.c diff --git a/gcc/config/i386/i386-builtins.cc b/gcc/config/i386/i386-builtins.cc index 28f404da288..e436ca4e5b1 100644 --- a/gcc/config/i386/i386-builtins.cc +++ b/gcc/config/i386/i386-builtins.cc @@ -662,19 +662,23 @@ ix86_init_mmx_sse_builtins (void) VOID_FTYPE_UNSIGNED_UNSIGNED, IX86_BUILTIN_MWAIT); /* AES */ - def_builtin_const (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2, + def_builtin_const (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2 + | OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, "__builtin_ia32_aesenc128", V2DI_FTYPE_V2DI_V2DI, IX86_BUILTIN_AESENC128); - def_builtin_const (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2, + def_builtin_const (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2 + | OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, "__builtin_ia32_aesenclast128", V2DI_FTYPE_V2DI_V2DI, IX86_BUILTIN_AESENCLAST128); - def_builtin_const (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2, + def_builtin_const (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2 + | OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, "__builtin_ia32_aesdec128", V2DI_FTYPE_V2DI_V2DI, IX86_BUILTIN_AESDEC128); - def_builtin_const (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2, + def_builtin_const (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2 + | OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_VAES, "__builtin_ia32_aesdeclast128", V2DI_FTYPE_V2DI_V2DI, IX86_BUILTIN_AESDECLAST128); diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 567248d6830..9a04bf4455b 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -12626,6 +12626,7 @@ ix86_check_builtin_isa_match (unsigned int fcode, OPTION_MASK_ISA2_AVXIFMA (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA2_AVX512BF16) or OPTION_MASK_ISA2_AVXNECONVERT + OPTION_MASK_ISA_AES or (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA2_VAES) where for each such pair it is sufficient if either of the ISAs is enabled, plus if it is ored with other options also those others. OPTION_MASK_ISA_MMX in bisa is satisfied also if TARGET_MMX_WITH_SSE. */ @@ -12649,7 +12650,8 @@ ix86_check_builtin_isa_match (unsigned int fcode, OPTION_MASK_ISA2_AVXIFMA); SHARE_BUILTIN (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512BF16, 0, OPTION_MASK_ISA2_AVXNECONVERT); - SHARE_BUILTIN (OPTION_MASK_ISA_AES, 0, 0, OPTION_MASK_ISA2_VAES); + SHARE_BUILTIN (OPTION_MASK_ISA_AES, 0, OPTION_MASK_ISA_AVX512VL, + OPTION_MASK_ISA2_VAES); isa = tmp_isa; isa2 = tmp_isa2; diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vaes-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-vaes-1.c new file mode 100644 index 00000000000..fabb170a031 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vaes-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mvaes -mno-avx512vl -mno-aes" } */ + +#include + +typedef long long v2di __attribute__((vector_size (16))); + +v2di +f1 (v2di x, v2di y) +{ + return __builtin_ia32_aesenc128 (x, y); /* { dg-error "needs isa option" } */ +}