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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id er14-20020a056402448e00b0051dd3d52814si4494794edb.633.2023.07.04.07.06.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 07:06:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=YqQ6mJyz; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3159F385771E for ; Tue, 4 Jul 2023 14:06:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3159F385771E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1688479587; bh=PzaxBDwCnA8sjr8Pye8dyc8TKXxseDMjMrC8B/VUPe8=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=YqQ6mJyzMQp8/1BGvfHh9ACLTZjjMQfso5GfSKy2HoKGrC3Jwl1jO4G/9hJHUfqna sefL+PXFcPmEJ0W533FwRAaYh80jnIvyCpjmTroEkBUW46gUTQWdE6QAj5Yep2tFXb +9X1VCYgOUvv5y/7XfYwfV87mbRKD4jc1omRPLDU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id C73A43858D35 for ; Tue, 4 Jul 2023 14:05:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C73A43858D35 X-IronPort-AV: E=McAfee;i="6600,9927,10760"; a="342718600" X-IronPort-AV: E=Sophos;i="6.01,180,1684825200"; d="scan'208";a="342718600" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jul 2023 07:05:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10760"; a="722089277" X-IronPort-AV: E=Sophos;i="6.01,180,1684825200"; d="scan'208";a="722089277" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga007.fm.intel.com with ESMTP; 04 Jul 2023 07:05:39 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 51B681005155; Tue, 4 Jul 2023 22:05:38 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com Subject: [PATCH v3] RISC-V: Fix one bug for floating-point static frm Date: Tue, 4 Jul 2023 22:05:36 +0800 Message-Id: <20230704140536.680044-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704055053.2308713-1-pan2.li@intel.com> References: <20230704055053.2308713-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770468048104487685?= X-GMAIL-MSGID: =?utf-8?q?1770499173241007187?= From: Pan Li This patch would like to fix one bug to align below items of spec. 1. By default, the RVV floating-point will take dyn mode. 2. DYN is invalid in FRM register for RVV floating-point. When mode switching the function entry and exit, it will take DYN as the frm mode. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn when FRM_MODE_DYN. (riscv_mode_entry): Take FRM_MODE_DYN as entry mode. (riscv_mode_exit): Likewise for exit mode. (riscv_mode_needed): Likewise for needed mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test. --- gcc/config/riscv/riscv.cc | 14 ++++++--- .../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++ 2 files changed, 41 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e4dc8115e69..ebc4db1aa94 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode, emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode))); break; case RISCV_FRM: - if (mode != FRM_MODE_NONE && mode != prev_mode) + if (mode != FRM_MODE_DYN && mode != prev_mode) { rtx scaler = gen_reg_rtx (SImode); rtx imm = gen_int_mode (mode, SImode); @@ -7697,7 +7697,9 @@ riscv_mode_needed (int entity, rtx_insn *insn) case RISCV_VXRM: return code >= 0 ? get_attr_vxrm_mode (insn) : VXRM_MODE_NONE; case RISCV_FRM: - return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE; + /* According to RVV 1.0 spec, all vector floating-point operations use + the dynamic rounding mode in the frm register. */ + return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN; default: gcc_unreachable (); } @@ -7774,7 +7776,9 @@ riscv_mode_entry (int entity) case RISCV_VXRM: return VXRM_MODE_NONE; case RISCV_FRM: - return FRM_MODE_NONE; + /* According to RVV 1.0 spec, all vector floating-point operations use + the dynamic rounding mode in the frm register. */ + return FRM_MODE_DYN; default: gcc_unreachable (); } @@ -7791,7 +7795,9 @@ riscv_mode_exit (int entity) case RISCV_VXRM: return VXRM_MODE_NONE; case RISCV_FRM: - return FRM_MODE_NONE; + /* According to RVV 1.0 spec, all vector floating-point operations use + the dynamic rounding mode in the frm register. */ + return FRM_MODE_DYN; default: gcc_unreachable (); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c new file mode 100644 index 00000000000..6d896e0953e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl); +} + +vfloat32m1_t +test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl); +} + +vfloat32m1_t +test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl); +} + +vfloat32m1_t +test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl); +} + +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */