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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id j8-20020a170906830800b0098ce1b37a89si13847809ejx.316.2023.07.04.05.27.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 05:27:02 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=VFHuFebI; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C3606385770B for ; Tue, 4 Jul 2023 12:27:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C3606385770B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1688473620; bh=OfOMrbqGKof1Y0kr4O3fbXNSkEfdEEm4tgRYt/JvKHk=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=VFHuFebIJr5DdPj35WaHhvPtMOYEO06wfsJcYR9zJij3/Zl5S7bIU7CLFn+1FTwOD 7crqE4BWoOYkgt1Ey83rvDXQVb1QB/nYdr9ao0QZOxY0FngDRS0qHmC2JvqOHz6IWe avLGFeLOkLWIkg8V62fI15QubEEvrrsy7Z6pdN2g= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 4892B3858D35 for ; Tue, 4 Jul 2023 12:26:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4892B3858D35 X-IronPort-AV: E=McAfee;i="6600,9927,10760"; a="360589785" X-IronPort-AV: E=Sophos;i="6.01,180,1684825200"; d="scan'208";a="360589785" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jul 2023 05:26:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10760"; a="718902499" X-IronPort-AV: E=Sophos;i="6.01,180,1684825200"; d="scan'208";a="718902499" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga002.jf.intel.com with ESMTP; 04 Jul 2023 05:26:13 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 9DF7A1006F21; Tue, 4 Jul 2023 20:26:12 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand Date: Tue, 4 Jul 2023 20:26:11 +0800 Message-Id: <20230704122611.4128668-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770492916901458357?= X-GMAIL-MSGID: =?utf-8?q?1770492916901458357?= From: Pan Li This patch would like to take FRM_DYN const rtx as the rounding mode operand according to the RVV spec, which takes the dyn as the only rounding mode for floating-point. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (function_expander::use_exact_insn): Use FRM_DYN instead of const0. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-vector-builtins.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 648c765a5d1..3a53b56effa 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3569,11 +3569,10 @@ function_expander::use_exact_insn (insn_code icode) if (base->has_rounding_mode_operand_p ()) add_input_operand (call_expr_nargs (exp) - 2); - /* TODO: Currently, we don't support intrinsic that is modeling rounding mode. - We add default rounding mode for the intrinsics that didn't model rounding - mode yet. */ + /* The RVV floating-point only support dynamic rounding mode in the + FRM register. */ if (opno != insn_data[icode].n_generator_args) - add_input_operand (Pmode, const0_rtx); + add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode)); return generate_insn (icode); }