diff mbox series

[v1] RISC-V: Use FRM_DYN when add the rounding mode operand

Message ID 20230704122611.4128668-1-pan2.li@intel.com
State Unresolved
Headers
Series [v1] RISC-V: Use FRM_DYN when add the rounding mode operand |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Li, Pan2 via Gcc-patches July 4, 2023, 12:26 p.m. UTC 
  From: Pan Li <pan2.li@intel.com>

This patch would like to take FRM_DYN const rtx as the rounding mode
operand according to the RVV spec, which takes the dyn as the only
rounding mode for floating-point.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins.cc
	(function_expander::use_exact_insn): Use FRM_DYN instead of const0.
---
 gcc/config/riscv/riscv-vector-builtins.cc | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

Comments

Robin Dapp July 4, 2023, 12:54 p.m. UTC | #1 
Hi Pan,

in general this looks good to me.  I would have expected the
change in the other patch I just looked at though ;)  Sure
it's intrinsics this time but the same principle. 

Regards
 Robin
juzhe.zhong@rivai.ai July 5, 2023, 2:07 a.m. UTC | #2 
LGTM.



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-07-04 20:26
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
From: Pan Li <pan2.li@intel.com>
 
This patch would like to take FRM_DYN const rtx as the rounding mode
operand according to the RVV spec, which takes the dyn as the only
rounding mode for floating-point.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
 
gcc/ChangeLog:
 
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_exact_insn): Use FRM_DYN instead of const0.
---
gcc/config/riscv/riscv-vector-builtins.cc | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
 
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 648c765a5d1..3a53b56effa 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3569,11 +3569,10 @@ function_expander::use_exact_insn (insn_code icode)
   if (base->has_rounding_mode_operand_p ())
     add_input_operand (call_expr_nargs (exp) - 2);
-  /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
-     We add default rounding mode for the intrinsics that didn't model rounding
-     mode yet.  */
+  /* The RVV floating-point only support dynamic rounding mode in the
+     FRM register.  */
   if (opno != insn_data[icode].n_generator_args)
-    add_input_operand (Pmode, const0_rtx);
+    add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
   return generate_insn (icode);
}
-- 
2.34.1
Kito Cheng July 5, 2023, 7:16 a.m. UTC | #3 
LGTM

On Wed, Jul 5, 2023 at 10:08 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-07-04 20:26
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to take FRM_DYN const rtx as the rounding mode
> operand according to the RVV spec, which takes the dyn as the only
> rounding mode for floating-point.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc
> (function_expander::use_exact_insn): Use FRM_DYN instead of const0.
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index 648c765a5d1..3a53b56effa 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -3569,11 +3569,10 @@ function_expander::use_exact_insn (insn_code icode)
>    if (base->has_rounding_mode_operand_p ())
>      add_input_operand (call_expr_nargs (exp) - 2);
> -  /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
> -     We add default rounding mode for the intrinsics that didn't model rounding
> -     mode yet.  */
> +  /* The RVV floating-point only support dynamic rounding mode in the
> +     FRM register.  */
>    if (opno != insn_data[icode].n_generator_args)
> -    add_input_operand (Pmode, const0_rtx);
> +    add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
>    return generate_insn (icode);
> }
> --
> 2.34.1
>
>
Li, Pan2 via Gcc-patches July 5, 2023, 2:27 p.m. UTC | #4 
Committed, thanks Juzhe and Kito.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Wednesday, July 5, 2023 3:16 PM
To: juzhe.zhong@rivai.ai
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand

LGTM

On Wed, Jul 5, 2023 at 10:08 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-07-04 20:26
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to take FRM_DYN const rtx as the rounding mode
> operand according to the RVV spec, which takes the dyn as the only
> rounding mode for floating-point.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc
> (function_expander::use_exact_insn): Use FRM_DYN instead of const0.
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index 648c765a5d1..3a53b56effa 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -3569,11 +3569,10 @@ function_expander::use_exact_insn (insn_code icode)
>    if (base->has_rounding_mode_operand_p ())
>      add_input_operand (call_expr_nargs (exp) - 2);
> -  /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
> -     We add default rounding mode for the intrinsics that didn't model rounding
> -     mode yet.  */
> +  /* The RVV floating-point only support dynamic rounding mode in the
> +     FRM register.  */
>    if (opno != insn_data[icode].n_generator_args)
> -    add_input_operand (Pmode, const0_rtx);
> +    add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
>    return generate_insn (icode);
> }
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 648c765a5d1..3a53b56effa 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3569,11 +3569,10 @@  function_expander::use_exact_insn (insn_code icode)
   if (base->has_rounding_mode_operand_p ())
     add_input_operand (call_expr_nargs (exp) - 2);
 
-  /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
-     We add default rounding mode for the intrinsics that didn't model rounding
-     mode yet.  */
+  /* The RVV floating-point only support dynamic rounding mode in the
+     FRM register.  */
   if (opno != insn_data[icode].n_generator_args)
-    add_input_operand (Pmode, const0_rtx);
+    add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
 
   return generate_insn (icode);
 }