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[8.43.85.97]) by mx.google.com with ESMTPS id x19-20020a1709065ad300b00992e0f4e85fsi4895453ejs.229.2023.07.04.01.42.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 01:42:56 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=lQyqWTuk; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 327433858409 for ; Tue, 4 Jul 2023 08:42:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 327433858409 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1688460175; bh=taoRumdWGBzCOl+tAbO4eARkXRCRYdliElsjgT04Ap8=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=lQyqWTukWQJz1aNgeB33AJtR0BbaCcP653LxmshPR2rI3MOEE3NfI1yzJaIQY+lV0 D+POAA5AcwW1yw5Bw6A72lfC9xaXbZFEk7TDQ5ZWIeYmnwSYPdmaWLdP5k73eN+6Ko HUKc84swReEqirUfjBI1Po6nAARChfmWVlsMHT2g= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 87CD83858D3C for ; Tue, 4 Jul 2023 08:42:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 87CD83858D3C X-IronPort-AV: E=McAfee;i="6600,9927,10760"; a="366554743" X-IronPort-AV: E=Sophos;i="6.01,180,1684825200"; d="scan'208";a="366554743" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jul 2023 01:42:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10760"; a="863342025" X-IronPort-AV: E=Sophos;i="6.01,180,1684825200"; d="scan'208";a="863342025" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga001.fm.intel.com with ESMTP; 04 Jul 2023 01:42:00 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 457101005700; Tue, 4 Jul 2023 16:41:59 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Refine the insn pattern of fsrm Date: Tue, 4 Jul 2023 16:41:58 +0800 Message-Id: <20230704084158.2976523-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770478817550202112?= X-GMAIL-MSGID: =?utf-8?q?1770478817550202112?= From: Pan Li This patch would like to introduce 2 new patter of fsrm with SImode, aka: 1. fsrmsi_backup 2. fsrmsi_restore Both patterns accept the imm and reg format, and then leverage the imm format instead of reg when RVV floating-point static rounding mode. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv.cc (riscv_emit_mode_set): Take frm imm insn. * config/riscv/vector.md (fsrm): Removed. (fsrmsi_backup): New define insn. (fsrmsi_restore): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-1.c: Adjust checker. * gcc.target/riscv/rvv/base/float-point-frm-insert-2.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-3.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-4.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-5.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: Ditto. Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 8 +--- gcc/config/riscv/vector.md | 38 ++++++++++--------- .../riscv/rvv/base/float-point-frm-insert-1.c | 2 +- .../riscv/rvv/base/float-point-frm-insert-2.c | 2 +- .../riscv/rvv/base/float-point-frm-insert-3.c | 2 +- .../riscv/rvv/base/float-point-frm-insert-4.c | 2 +- .../riscv/rvv/base/float-point-frm-insert-5.c | 2 +- .../riscv/rvv/base/float-point-frm-insert-6.c | 2 +- 8 files changed, 28 insertions(+), 30 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 37f96f8a238..8342e7dd031 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7671,13 +7671,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode, break; case RISCV_FRM: if (mode != FRM_MODE_DYN && mode != prev_mode) - { - rtx scaler = gen_reg_rtx (SImode); - rtx imm = gen_int_mode (mode, SImode); - - emit_insn (gen_movsi (scaler, imm)); - emit_insn (gen_fsrm (scaler, scaler)); - } + emit_insn (gen_fsrmsi_restore (gen_int_mode (mode, SImode))); break; default: gcc_unreachable (); diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 2864475b35a..13bc63a50fb 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -578,24 +578,28 @@ (define_insn "vxrmsi" (set_attr "mode" "SI")]) ;; Set FRM -(define_insn "fsrm" - [ - (set - (reg:SI FRM_REGNUM) - (unspec:SI - [ - (match_operand:SI 0 "register_operand" "=&r") - (match_operand:SI 1 "register_operand" "r") - ] UNSPEC_FSRM - ) - ) - ] +(define_insn "fsrmsi_backup" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (reg:SI FRM_REGNUM)) + (set (reg:SI FRM_REGNUM) + (match_operand:SI 1 "reg_or_int_operand" "r,i"))] "TARGET_VECTOR" - "fsrm\t%0,%1" - [ - (set_attr "type" "wrfrm") - (set_attr "mode" "SI") - ] + "@ + fsrm\t%0,%1 + fsrmi\t%0,%1" + [(set_attr "type" "wrfrm,wrfrm") + (set_attr "mode" "SI")] +) + +(define_insn "fsrmsi_restore" + [(set (reg:SI FRM_REGNUM) + (match_operand:SI 0 "reg_or_int_operand" "r,i"))] + "TARGET_VECTOR" + "@ + fsrm\t%0 + fsrmi\t%0" + [(set_attr "type" "wrfrm,wrfrm") + (set_attr "mode" "SI")] ) ;; ----------------------------------------------------------------- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c index 732e0305a3d..a59ffe2c65e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c @@ -28,4 +28,4 @@ test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, } /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c index 72e5d2084b3..3254d6a40b9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-2.c @@ -11,4 +11,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { } /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c index c9e8d0a6eaf..f8679c2f716 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-3.c @@ -11,4 +11,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { } /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c index a288e0be628..d8a15f30c5a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-4.c @@ -20,4 +20,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl, } /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 4 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c index bb77a6efc62..cf603920946 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-5.c @@ -20,4 +20,4 @@ test_float_point_frm_insert (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl, } /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v+[0-9]+} 4 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c index 6d896e0953e..efd89ccfc3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c @@ -28,4 +28,4 @@ test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2, } /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */ -/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */ +/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */