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[8.43.85.97]) by mx.google.com with ESMTPS id h13-20020a170906718d00b00992e23ef220si4024764ejk.567.2023.07.03.05.34.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jul 2023 05:34:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 322F53858D32 for ; Mon, 3 Jul 2023 12:34:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 150813858D1E for ; Mon, 3 Jul 2023 12:33:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 150813858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp85t1688387625t8p258uv Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 03 Jul 2023 20:33:43 +0800 (CST) X-QQ-SSF: 01400000000000G0T000000A0000000 X-QQ-FEAT: 90EFqYDyPxB7nSIaE+JVQ2oTHIndYCfIrKD+sQLh7qJd3gRpExvqXTvPNgLKQ 2/wkcNpKt4R1xSGg4qMKmK+3AtZwcX8V0q8tGj+z2p/8dSCpUF9dyUsIA7aZqqML4v0bWje 6BXKt0t1aiG8fPr+T9n+sBS8lR987/5ztEKMAEnYEzcyaKmi1kbhaarQfKP/AlTzaWoPIfX PrmcRXZABjrCE9MRs0XfbGOfSCmZiYy0qxUj29D+h/HF/26OE26LWqiVV4RCJMcH7qwWeW+ GXNyfdNO128R44MKVcN/QmTKV7iDFZW+jMMfJmF20f0lNzYWE2utNf76Y1O8SrIiEoryi+/ 9duUAG4lFOW46MN7eiZd9/xqkjYmrx3kv9IzhVsuaVlm0G65acoPKkNd7py8v8S/grF3J/x zayja2CCwe0= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 16343776888342302340 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [VSETVL PASS] RISC-V: Optimize local AVL propagation Date: Mon, 3 Jul 2023 20:33:42 +0800 Message-Id: <20230703123342.2341414-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770402787419506581?= X-GMAIL-MSGID: =?utf-8?q?1770402787419506581?= I recently noticed that current VSETVL pass has a unnecessary restriction on local AVL propgation. Consider this following case: + insn 1: vsetvli a5,a3,e8,mf4,ta,mu + insn 2: vsetvli zero,a5,e32,m1,ta,ma + ... + vle32.v v1,0(a1) + vsetvli a2,zero,e32,m1,ta,ma + vadd.vv v1,v1,v1 + vsetvli zero,a5,e32,m1,ta,ma + vse32.v v1,0(a0) + ... + insn 3: sub a3,a3,a5 + ... We failed to elide insn 2 (vsetvl insn) since insn 3 is modifying "a3" AVL. Actually, we don't really care about insn 3 since we should only check and make sure there is no insn between insn 1 and insn 2 that modifies "a3" AVL. Then, we can propgate AVL "a3" from insn 1 to insn 2. Finally, insn 2 is eliminated. After this patch: + insn 1: vsetvli a5,a3,e8,mf4,ta,ma + ... + vle32.v v1,0(a1) + vsetvli a2,zero,e32,m1,ta,ma + vadd.vv v1,v1,v1 + vsetvli zero,a5,e32,m1,ta,ma + vse32.v v1,0(a0) + ... + insn 3: sub a3,a3,a5 + ... gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vector_insn_info::parse_insn): Add early break. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_prop-1.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 22 +++++++++++++++++++ .../gcc.target/riscv/rvv/vsetvl/avl_prop-1.c | 21 ++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 2d576e8d5c1..ab47901e23f 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -2025,6 +2025,28 @@ vector_insn_info::parse_insn (insn_info *insn) real_insn_and_same_bb_p (i, get_insn ()->bb ()); i = i->next_nondebug_insn ()) { + /* Consider this following sequence: + + insn 1: vsetvli a5,a3,e8,mf4,ta,mu + insn 2: vsetvli zero,a5,e32,m1,ta,ma + ... + vle32.v v1,0(a1) + vsetvli a2,zero,e32,m1,ta,ma + vadd.vv v1,v1,v1 + vsetvli zero,a5,e32,m1,ta,ma + vse32.v v1,0(a0) + ... + insn 3: sub a3,a3,a5 + ... + + We can local AVL propagate "a3" from insn 1 to insn 2 + if no insns between insn 1 and insn 2 modify "a3 even + though insn 3 modifies "a3". + Otherwise, we can't perform local AVL propagation. + + Early break if we reach the insn 2. */ + if (!before_p (i, insn)) + break; if (find_access (i->defs (), REGNO (new_info.get_avl ()))) { modified_p = true; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c new file mode 100644 index 00000000000..19ea0f14df5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +void +foo (void *a, void *b, void *c, size_t n) +{ + for (size_t vl; n > 0; n -= vl, a += vl, b += vl * 4, c += vl) + { + vl = __riscv_vsetvl_e8mf4 (n); + vint32m1_t vec_b = __riscv_vle32_v_i32m1 (b, vl); + vint32m1_t vec_a = __riscv_vadd_vv_i32m1 (vec_b, vec_b, __riscv_vsetvlmax_e32m1 ()); + __riscv_vse32_v_i32m1 (a, vec_a, vl); + } +} + +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */