diff mbox series

[v1] RISC-V: Refactor vxrm_mode attr for type attr equal

Message ID 20230629060054.617743-1-pan2.li@intel.com
State Unresolved
Headers
Series [v1] RISC-V: Refactor vxrm_mode attr for type attr equal |

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Context Check Description
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Commit Message

Li, Pan2 via Gcc-patches June 29, 2023, 6 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

This patch would like to refactor the vxrm_mode attr for duplicated
eq_attr condition. The common condition of attr is extraced to one
place instead of many places.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/vector.md: Refactor the common condition.
---
 gcc/config/riscv/vector.md | 39 ++++++++++++++++++++++----------------
 1 file changed, 23 insertions(+), 16 deletions(-)

Comments

juzhe.zhong@rivai.ai June 29, 2023, 6:12 a.m. UTC | #1 
It's meaningless. Drop this patch.



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-06-29 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang; jeffreyalaw
Subject: [PATCH v1] RISC-V: Refactor vxrm_mode attr for type attr equal
From: Pan Li <pan2.li@intel.com>
 
This patch would like to refactor the vxrm_mode attr for duplicated
eq_attr condition. The common condition of attr is extraced to one
place instead of many places.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
 
gcc/ChangeLog:
 
* config/riscv/vector.md: Refactor the common condition.
---
gcc/config/riscv/vector.md | 39 ++++++++++++++++++++++----------------
1 file changed, 23 insertions(+), 16 deletions(-)
 
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 406f96439ec..ebb7648b4df 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -445,22 +445,29 @@ (define_attr "avl_type" ""
;; Defines rounding mode of an fixed-point operation.
(define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
-  (cond [(and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-       (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_RNU"))
- (const_string "rnu")
-
- (and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-       (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_RNE"))
- (const_string "rne")
-
- (and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-       (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_RDN"))
- (const_string "rdn")
-
- (and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-       (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_ROD"))
- (const_string "rod")]
- (const_string "none")))
+  (cond
+    [
+      (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
+      (cond
+ [
+   (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU")
+   (const_string "rnu")
+
+   (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE")
+   (const_string "rne")
+
+   (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN")
+   (const_string "rdn")
+
+   (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD")
+   (const_string "rod")
+ ]
+ (const_string "none")
+      )
+    ]
+    (const_string "none")
+  )
+)
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
-- 
2.34.1
juzhe.zhong@rivai.ai June 29, 2023, 6:23 a.m. UTC | #2 
Oh. I see. You are not only changing the format. Sorry about that I didn't notice.

originally, each rounding mode has "vsalu,vaalu,vsmul,vsshift,vnclip"

Now, you change all rounding mode sharing same "vsalu,vaalu,vsmul,vsshift,vnclip".

When we want to remove some of the insn, we don't need to remove 4 places.

LGTM. Thanks.


juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-06-29 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang; jeffreyalaw
Subject: [PATCH v1] RISC-V: Refactor vxrm_mode attr for type attr equal
From: Pan Li <pan2.li@intel.com>
 
This patch would like to refactor the vxrm_mode attr for duplicated
eq_attr condition. The common condition of attr is extraced to one
place instead of many places.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
 
gcc/ChangeLog:
 
* config/riscv/vector.md: Refactor the common condition.
---
gcc/config/riscv/vector.md | 39 ++++++++++++++++++++++----------------
1 file changed, 23 insertions(+), 16 deletions(-)
 
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 406f96439ec..ebb7648b4df 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -445,22 +445,29 @@ (define_attr "avl_type" ""
;; Defines rounding mode of an fixed-point operation.
(define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
-  (cond [(and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-       (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_RNU"))
- (const_string "rnu")
-
- (and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-       (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_RNE"))
- (const_string "rne")
-
- (and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-       (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_RDN"))
- (const_string "rdn")
-
- (and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-       (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_ROD"))
- (const_string "rod")]
- (const_string "none")))
+  (cond
+    [
+      (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
+      (cond
+ [
+   (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU")
+   (const_string "rnu")
+
+   (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE")
+   (const_string "rne")
+
+   (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN")
+   (const_string "rdn")
+
+   (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD")
+   (const_string "rod")
+ ]
+ (const_string "none")
+      )
+    ]
+    (const_string "none")
+  )
+)
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
-- 
2.34.1
Jeff Law June 29, 2023, 8:58 p.m. UTC | #3 
On 6/29/23 00:00, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to refactor the vxrm_mode attr for duplicated
> eq_attr condition. The common condition of attr is extraced to one
> place instead of many places.
> 
> Signed-off-by: Pan Li <pan2.li@intel.com>
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/vector.md: Refactor the common condition.
OK
jeff
Li, Pan2 via Gcc-patches June 30, 2023, 11:15 a.m. UTC | #4 
Committed, thanks Jeff and Juzhe.

Pan

-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com> 
Sent: Friday, June 30, 2023 4:58 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Refactor vxrm_mode attr for type attr equal



On 6/29/23 00:00, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to refactor the vxrm_mode attr for duplicated
> eq_attr condition. The common condition of attr is extraced to one
> place instead of many places.
> 
> Signed-off-by: Pan Li <pan2.li@intel.com>
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/vector.md: Refactor the common condition.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 406f96439ec..ebb7648b4df 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -445,22 +445,29 @@  (define_attr "avl_type" ""
 ;; Defines rounding mode of an fixed-point operation.
 
 (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
-  (cond [(and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-	      (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_RNU"))
-	 (const_string "rnu")
-
-	 (and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-	      (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_RNE"))
-	 (const_string "rne")
-
-	 (and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-	      (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_RDN"))
-	 (const_string "rdn")
-
-	 (and (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
-	      (match_test "INTVAL(operands[9]) == riscv_vector::VXRM_ROD"))
-	 (const_string "rod")]
-	 (const_string "none")))
+  (cond
+    [
+      (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip")
+      (cond
+	[
+	  (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU")
+	  (const_string "rnu")
+
+	  (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE")
+	  (const_string "rne")
+
+	  (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN")
+	  (const_string "rdn")
+
+	  (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD")
+	  (const_string "rod")
+	]
+	(const_string "none")
+      )
+    ]
+    (const_string "none")
+  )
+)
 
 ;; -----------------------------------------------------------------
 ;; ---- Miscellaneous Operations