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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id r6-20020a170906c28600b00992860fb029si368386ejz.642.2023.06.28.02.49.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 02:49:07 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AAF05385840C for ; Wed, 28 Jun 2023 09:48:38 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id EF3713858C36 for ; Wed, 28 Jun 2023 09:48:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EF3713858C36 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp91t1687945676t9jbsuka Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 28 Jun 2023 17:47:54 +0800 (CST) X-QQ-SSF: 01400000000000G0S000000A0000000 X-QQ-FEAT: +ynUkgUhZJmcMo3d3ijkA1yU/RcUiTbtmDX8/AcvGx+ZCagxzJgakJubFEAk3 ZjsZy2dMQklln/KzEuvZSmVxh60WUT800mRxDCDV7hAvpvmQIyIGKgFvC9g2Q9InbDOsKxg MCOVebUh8JWoAQq45h8L+8MequyLtpQjQMgAfx2JSZG2ezDETpT/Szs9WT5NmBC3Nbk2Our ug6pGyJiDNICKRyRRpRsduGhThsUdalq8QrtwdzUopPgFNVDak3n2qnDEvkueeRZrsdW1n5 dN/6InKUWi1Ugad//QpADe/MZdthzAma4KzjaHGcpJNsYnE+D20iEWswh/HzxBZxHevk5tf x1uVsKf72FBq+BkWM4rn3AaBnPEfzKPu4pM6CaXFcoeYYOhs42+AWS8FFQyVflOQGuLwcfT 03WeF/4efCixk1k3djjiJoyc9lpEAHBI X-QQ-GoodBg: 2 X-BIZMAIL-ID: 4857543051176544040 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI Date: Wed, 28 Jun 2023 17:47:52 +0800 Message-Id: <20230628094752.332289-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_35_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769939399980988242?= X-GMAIL-MSGID: =?utf-8?q?1769939399980988242?= This bug blocks the following patches. GCC doesn't know RVV is using compact mask model. Consider this following case: #define N 16 int main () { int8_t mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; int8_t out[N] = {0}; for (int8_t i = 0; i < N; ++i) if (mask[i]) out[i] = i; for (int8_t i = 0; i < N; ++i) { if (mask[i]) assert (out[i] == i); else assert (out[i] == 0); } } Before this patch, the pre-calculated mask in constant memory pool: .LC1: .byte 68 ====> 0b01000100 This is incorrect, such case failed in execution. After this patch: .LC1: .byte 10 ====> 0b1010 Pass on exection. After diging into this issue, I figure such bug only happens on VNx1BI, VNx2BI and VNx4BI. The reason as follows: /* Return true if the BITSIZE and PRECISION are not equal. This helper function tests BITSIZE and PRECISION on RVV mask modes. For VNx1BI/VNx2BI/VNx4BI modes, since they are having same BYTESIZE with VNx8BI and compiler can not differentiate them when they are having same BYTESIZE which will cause incorrect DCE/DSE for them. To differentiate VNx1BI/VNx2BI/VNx4BI/VNx8BI, we use ADJUST_PRECISION in riscv-modes.def to adjust different PRECISION for them. Such approach works fine that compiler can differentiate them, but it causes incorrect organization of bitmask memory layout. E.g mask = { 0, -1 } for VNx2BI, the PRECISION will let compiler adjust bitmask memory layout: 0b0001 which is incorrect for RVV. Instead, we want to see the correct bitmask memory layout: 0b01. In this situation, we let RISC-V backend to re-organize the bitmask memory layout in "mov" pattern. */ So here we add a helper function "bitsize_precision_unequal_p" to force RISC-V backend re-organize bitmask memory layout of VNx1BI, VNx2BI, VNx4BI since their PRECISION != BITSIZE. I don't use mode == VNx1BI || mode == VNx2BI || mode == VNx4BI since we are going to have VLS modes. maybe_ne (GET_MODE_BITSIZE (mode), GET_MODE_PRECISION (mode)) can cover any case including VLA and VLS. gcc/ChangeLog: * config/riscv/riscv-v.cc (rvv_builder::get_compact_mask): New function. (expand_const_vector): Fix bug. * config/riscv/riscv.cc (bitsize_precision_unequal_p): New function. (riscv_const_insns): Fix bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c: New test. --- gcc/config/riscv/riscv-v.cc | 64 +++++++++++++++++-- gcc/config/riscv/riscv.cc | 36 +++++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-1.c | 23 +++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-10.c | 22 +++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-11.c | 23 +++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-12.c | 23 +++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-13.c | 23 +++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-14.c | 24 +++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-2.c | 23 +++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-3.c | 23 +++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-4.c | 23 +++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-5.c | 25 ++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-6.c | 27 ++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-7.c | 30 +++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-8.c | 30 +++++++++ .../riscv/rvv/autovec/vls-vlmax/bitmask-9.c | 30 +++++++++ 16 files changed, 444 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index adb8d7d36a5..5da0dc5e998 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -291,6 +291,7 @@ public: bool single_step_npatterns_p () const; bool npatterns_all_equal_p () const; + rtx get_compact_mask () const; machine_mode new_mode () const { return m_new_mode; } scalar_mode inner_mode () const { return m_inner_mode; } @@ -505,6 +506,47 @@ rvv_builder::npatterns_all_equal_p () const return true; } +/* Generate the compact mask. + + E.g: mask = { 0, -1 }, mode = VNx2BI, bitsize = 128bits. + + GCC by default will generate the mask = 0b00000001xxxxx. + + However, it's not expected mask for RVV since RVV + prefers the compact mask = 0b10xxxxx. +*/ +rtx +rvv_builder::get_compact_mask () const +{ + /* If TARGET_MIN_VLEN == 32, the minimum LMUL = 1/4. + Otherwise, the minimum LMUL = 1/8. */ + unsigned min_lmul = TARGET_MIN_VLEN == 32 ? 4 : 8; + unsigned min_container_size + = BYTES_PER_RISCV_VECTOR.to_constant () / min_lmul; + unsigned container_size = MAX (CEIL (npatterns (), 8), min_container_size); + machine_mode container_mode + = get_vector_mode (QImode, container_size).require (); + + unsigned nunits = GET_MODE_NUNITS (container_mode).to_constant (); + rtvec v = rtvec_alloc (nunits); + for (unsigned i = 0; i < nunits; i++) + RTVEC_ELT (v, i) = const0_rtx; + + unsigned char b = 0; + for (unsigned i = 0; i < npatterns (); i++) + { + if (INTVAL (elt (i))) + b = b | (1 << (i % 8)); + + if ((i > 0 && (i % 8) == 7) || (i == (npatterns () - 1))) + { + RTVEC_ELT (v, ((i + 7) / 8) - 1) = gen_int_mode (b, QImode); + b = 0; + } + } + return gen_rtx_CONST_VECTOR (container_mode, v); +} + static unsigned get_sew (machine_mode mode) { @@ -1141,11 +1183,23 @@ expand_const_vector (rtx target, rtx src) if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) { rtx elt; - gcc_assert ( - const_vec_duplicate_p (src, &elt) - && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx))); - rtx ops[] = {target, src}; - emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); + unsigned int nelts; + if (const_vec_duplicate_p (src, &elt)) + { + rtx ops[] = {target, src}; + emit_vlmax_insn (code_for_pred_mov (mode), RVV_UNOP, ops); + } + else if (GET_MODE_NUNITS (mode).is_constant (&nelts)) + { + rvv_builder builder (mode, nelts, 1); + for (unsigned int i = 0; i < nelts; i++) + builder.quick_push (CONST_VECTOR_ELT (src, i)); + rtx mask = builder.get_compact_mask (); + rtx mem = validize_mem (force_const_mem (GET_MODE (mask), mask)); + emit_move_insn (target, gen_rtx_MEM (mode, XEXP (mem, 0))); + } + else + gcc_unreachable (); return; } diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 280aa0b33b9..13a9f98f30a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1244,6 +1244,36 @@ riscv_address_insns (rtx x, machine_mode mode, bool might_split_p) return n; } +/* Return true if the BITSIZE and PRECISION are not equal. + + This helper function tests BITSIZE and PRECISION on RVV mask modes. + + For VNx1BI/VNx2BI/VNx4BI modes, since they are having same BYTESIZE + with VNx8BI and compiler can not differentiate them when they are having + same BYTESIZE which will cause incorrect DCE/DSE for them. + + To differentiate VNx1BI/VNx2BI/VNx4BI/VNx8BI, we use ADJUST_PRECISION + in riscv-modes.def to adjust different PRECISION for them. + + Such approach works fine that compiler can differentiate them, but it causes + incorrect organization of bitmask memory layout. + + E.g mask = { 0, -1 } for VNx2BI, the PRECISION will let compiler adjust + bitmask memory layout: 0b0001 which is incorrect for RVV. + + Instead, we want to see the correct bitmask memory layout: 0b01. + In this situation, we let RISC-V backend to re-organize the bitmask + memory layout in "mov" pattern. +*/ +static bool +bitsize_precision_unequal_p (machine_mode mode) +{ + /* We don't need to worry about non-BOOL vector modes for RVV. */ + if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL) + return false; + return maybe_ne (GET_MODE_BITSIZE (mode), GET_MODE_PRECISION (mode)); +} + /* Return the number of instructions needed to load constant X. Return 0 if X isn't a valid constant. */ @@ -1323,6 +1353,12 @@ riscv_const_insns (rtx x) return 1 + 4; /*vmv.v.x + memory access. */ } } + + /* GCC doesn't known RVV is using compact model of mask, + we should by default handle mask in mov pattern. */ + if (bitsize_precision_unequal_p (GET_MODE (x))) + /* TODO: We can adjust it according real cost model of vlm.v. */ + return 1; } /* TODO: We may support more const vector in the future. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c new file mode 100644 index 00000000000..81229fd62b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-1.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include +#include +#define N 16 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int64_t out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c new file mode 100644 index 00000000000..d891f3c16e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-10.c @@ -0,0 +1,22 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */ +#include +#include +#define N 16 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int8_t out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c new file mode 100644 index 00000000000..535641443ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-11.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include +#include +#define N 4 + +int +main () +{ + int mask[N] = {0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c new file mode 100644 index 00000000000..a7c12c3797b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-12.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m2" } */ + +#include +#include +#define N 8 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c new file mode 100644 index 00000000000..726238c1cd8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-13.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m4" } */ + +#include +#include +#define N 16 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c new file mode 100644 index 00000000000..c369cf0b268 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-14.c @@ -0,0 +1,24 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3 --param riscv-autovec-lmul=m8" } */ + +#include +#include +#define N 32 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c new file mode 100644 index 00000000000..a23e47171bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-2.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include +#include +#define N 16 + +int +main () +{ + int mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c new file mode 100644 index 00000000000..6ea8fdd89c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-3.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include +#include +#define N 16 + +int +main () +{ + int16_t mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int16_t out[N] = {0}; + for (int16_t i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int16_t i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c new file mode 100644 index 00000000000..2d97c26abfd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-4.c @@ -0,0 +1,23 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax -O3" } */ + +#include +#include +#define N 16 + +int +main () +{ + int8_t mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int8_t out[N] = {0}; + for (int8_t i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int8_t i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c new file mode 100644 index 00000000000..b89b70e99a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-5.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3" } */ + +#include +#include + +#define N 32 + +int +main () +{ + int8_t mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int8_t out[N] = {0}; + for (int8_t i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int8_t i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c new file mode 100644 index 00000000000..ac8d91e793b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-6.c @@ -0,0 +1,27 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -O3" } */ + +#include +#include + +#define N 64 + +int +main () +{ + int8_t mask[N] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int8_t out[N] = {0}; + for (int8_t i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int8_t i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c new file mode 100644 index 00000000000..f538db23b1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-7.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ + +#include +#include + +#define N 128 + +int +main () +{ + uint8_t mask[N] + = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + uint8_t out[N] = {0}; + for (uint8_t i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (uint8_t i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c new file mode 100644 index 00000000000..5abb34c1686 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-8.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ + +#include +#include + +#define N 128 + +int +main () +{ + int mask[N] + = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c new file mode 100644 index 00000000000..6fdaa516534 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/bitmask-9.c @@ -0,0 +1,30 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "--param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m8 -O3" } */ + +#include +#include + +#define N 128 + +int +main () +{ + int64_t mask[N] + = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1}; + int64_t out[N] = {0}; + for (int i = 0; i < N; ++i) + if (mask[i]) + out[i] = i; + for (int i = 0; i < N; ++i) + { + if (mask[i]) + assert (out[i] == i); + else + assert (out[i] == 0); + } +}