diff mbox series

RISC-V: force arg and target to reg rtx under -O0

Message ID 20230625030837.23389-1-xuli1@eswincomputing.com
State Unresolved
Headers
Series RISC-V: force arg and target to reg rtx under -O0 |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Li Xu June 25, 2023, 3:08 a.m. UTC 
  arg and target should be expanded to reg rtx during expand pass.

Consider this following case:
void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
  vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
}

Compilation fails with:
test.c: In function 'test_vlmul_ext_v_i8mf8_i8mf4':
test.c:5:1: error: unrecognizable insn:
    5 | }
      | ^
(insn 30 29 0 2 (set (mem/c:VNx2QI (reg/f:DI 143) [0 x+0 S[2, 2] A32])
        (mem/c:VNx2QI (reg/f:DI 148) [0 op1+0 S[2, 2] A16])) "test.c":4:18 -1
     (nil))
during RTL pass: vregs
test.c:5:1: internal compiler error: in extract_insn, at recog.cc:2791
0x7c61b8 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
        ../.././riscv-gcc/gcc/rtl-error.cc:108
0x7c61d7 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        ../.././riscv-gcc/gcc/rtl-error.cc:116
0xed58a7 extract_insn(rtx_insn*)
        ../.././riscv-gcc/gcc/recog.cc:2791
0xb7f789 instantiate_virtual_regs_in_insn
        ../.././riscv-gcc/gcc/function.cc:1611
0xb7f789 instantiate_virtual_regs
        ../.././riscv-gcc/gcc/function.cc:1984

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins-bases.cc: force arg and target to reg rtx.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vlmul_ext-2.c: New test.
---
 gcc/config/riscv/riscv-vector-builtins-bases.cc       | 5 ++++-
 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c | 8 ++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c

Comments

juzhe.zhong@rivai.ai June 25, 2023, 3:43 a.m. UTC | #1 
Hi, Li.
Appreciate for catching this!

I think it's better:
-emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src));
+emit_move_insn (gen_lowpart (e.vector_mode (), e.target), src);
do this to fix this issue.

Thanks.


juzhe.zhong@rivai.ai
 
From: Li Xu
Date: 2023-06-25 11:08
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH] RISC-V: force arg and target to reg rtx under -O0
arg and target should be expanded to reg rtx during expand pass.
 
Consider this following case:
void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
  vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
}
 
Compilation fails with:
test.c: In function 'test_vlmul_ext_v_i8mf8_i8mf4':
test.c:5:1: error: unrecognizable insn:
    5 | }
      | ^
(insn 30 29 0 2 (set (mem/c:VNx2QI (reg/f:DI 143) [0 x+0 S[2, 2] A32])
        (mem/c:VNx2QI (reg/f:DI 148) [0 op1+0 S[2, 2] A16])) "test.c":4:18 -1
     (nil))
during RTL pass: vregs
test.c:5:1: internal compiler error: in extract_insn, at recog.cc:2791
0x7c61b8 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
        ../.././riscv-gcc/gcc/rtl-error.cc:108
0x7c61d7 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        ../.././riscv-gcc/gcc/rtl-error.cc:116
0xed58a7 extract_insn(rtx_insn*)
        ../.././riscv-gcc/gcc/recog.cc:2791
0xb7f789 instantiate_virtual_regs_in_insn
        ../.././riscv-gcc/gcc/function.cc:1611
0xb7f789 instantiate_virtual_regs
        ../.././riscv-gcc/gcc/function.cc:1984
 
gcc/ChangeLog:
 
        * config/riscv/riscv-vector-builtins-bases.cc: force arg and target to reg rtx.
 
gcc/testsuite/ChangeLog:
 
        * gcc.target/riscv/rvv/base/vlmul_ext-2.c: New test.
---
gcc/config/riscv/riscv-vector-builtins-bases.cc       | 5 ++++-
gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c | 8 ++++++++
2 files changed, 12 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index c6c53dc13a5..f135f7971fa 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1567,7 +1567,10 @@ public:
   {
     tree arg = CALL_EXPR_ARG (e.exp, 0);
     rtx src = expand_normal (arg);
-    emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src));
+    if (MEM_P (e.target))
+      e.target = force_reg (GET_MODE (e.target), e.target);
+    emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target),
+      MEM_P (src) ? force_reg (GET_MODE (src), src) : src));
     return e.target;
   }
};
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
new file mode 100644
index 00000000000..2b088b53546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+
+#include "riscv_vector.h"
+
+void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
+  vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
+}
-- 
2.17.1
Jeff Law June 25, 2023, 12:50 p.m. UTC | #2 
On 6/24/23 21:43, juzhe.zhong@rivai.ai wrote:
> Hi, Li.
> Appreciate for catching this!
> 
> I think it's better:
> -emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src));
> +emit_move_insn (gen_lowpart (e.vector_mode (), e.target), src);
> do this to fix this issue.
Agreed.  Assuming a variant fixing it this way passes testing, it's OK 
for the trunk.

jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index c6c53dc13a5..f135f7971fa 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1567,7 +1567,10 @@  public:
   {
     tree arg = CALL_EXPR_ARG (e.exp, 0);
     rtx src = expand_normal (arg);
-    emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src));
+    if (MEM_P (e.target))
+      e.target = force_reg (GET_MODE (e.target), e.target);
+    emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target),
+      MEM_P (src) ? force_reg (GET_MODE (src), src) : src));
     return e.target;
   }
 };
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
new file mode 100644
index 00000000000..2b088b53546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-2.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O0" } */
+
+#include "riscv_vector.h"
+
+void test_vlmul_ext_v_i8mf8_i8mf4(vint8mf8_t op1) {
+  vint8mf4_t res = __riscv_vlmul_ext_v_i8mf8_i8mf4(op1);
+}