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[8.43.85.97]) by mx.google.com with ESMTPS id op11-20020a170906bceb00b00977d56f47f9si7843839ejb.564.2023.06.13.19.16.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 19:16:47 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Y4w+Fyzp; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9AC02385840D for ; Wed, 14 Jun 2023 02:16:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9AC02385840D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686709006; bh=Oz0nYOliTmFQ/l2RBXFNp3v+2SixVlfJsxMqDySwKR4=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=Y4w+FyzpHn63hhep7jU1Dvv3E0FtZeN7HjTG5ETDXA4vZtLE/FXFWNMl7/Rhg3TV8 wXDIeqpQDa27tTlwhWRYbAdZg2dKDi4PpvvJqk64v3Buk5MIVrvRYqxP5IwTQSKTbj g6k6uOexG5wGtbkICtqvRWOV3+t9AFZmxfXC6O9w= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 337993858CDA for ; Wed, 14 Jun 2023 02:16:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 337993858CDA X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="355995690" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="355995690" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 19:16:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10740"; a="706029080" X-IronPort-AV: E=Sophos;i="6.00,241,1681196400"; d="scan'208";a="706029080" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga007.jf.intel.com with ESMTP; 13 Jun 2023 19:15:59 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 3103B10054EF; Wed, 14 Jun 2023 10:15:59 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split Date: Wed, 14 Jun 2023 10:15:57 +0800 Message-Id: <20230614021557.1691461-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768642584117243841?= X-GMAIL-MSGID: =?utf-8?q?1768642584117243841?= From: Pan Li This patch is considered as the follow up of the below PATCH. https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621347.html We aligned the predictor style for the define_insn_and_split suggested by Kito. To avoid potential issues before we hit. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/autovec-opt.md: Align the predictor sytle. * config/riscv/autovec.md: Ditto. Signed-off-by: Pan Li --- gcc/config/riscv/autovec-opt.md | 20 ++++++++++---------- gcc/config/riscv/autovec.md | 24 ++++++++++++------------ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index aef28e445e1..fb1b07205aa 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -37,9 +37,9 @@ (define_insn_and_split "@pred_single_widen_mul" (match_operand: 4 "register_operand" " vr, vr")) (match_operand:VWEXTI 3 "register_operand" " vr, vr")) (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_vf2 (, mode); @@ -132,9 +132,9 @@ (define_insn_and_split "*not" (bitmanip_bitwise:VB (not:VB (match_operand:VB 2 "register_operand" " vr")) (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_not (, mode); @@ -159,9 +159,9 @@ (define_insn_and_split "*n" (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr") (match_operand:VB 2 "register_operand" " vr"))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_n (, mode); @@ -346,9 +346,9 @@ (define_insn_and_split "*vtrunc" (match_operand:VWEXTI 1 "register_operand" " vr,vr") (any_extend:VWEXTI (match_operand: 2 "vector_shift_operand" " vr,vk")))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_narrow (, mode); @@ -364,9 +364,9 @@ (define_insn_and_split "*trunc" (any_shiftrt:VWEXTI (match_operand:VWEXTI 1 "register_operand" " vr") (match_operand: 2 "csr_operand" " rK"))))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { operands[2] = gen_lowpart (Pmode, operands[2]); diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index eadc2c5b595..c23a625afe1 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -155,9 +155,9 @@ (define_insn_and_split "3" (any_shift:VI (match_operand:VI 1 "register_operand" " vr") (match_operand: 2 "csr_operand" " rK")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { operands[2] = gen_lowpart (Pmode, operands[2]); @@ -180,9 +180,9 @@ (define_insn_and_split "v3" (any_shift:VI (match_operand:VI 1 "register_operand" " vr,vr") (match_operand:VI 2 "vector_shift_operand" " vr,vk")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { riscv_vector::emit_vlmax_insn (code_for_pred (, mode), @@ -205,9 +205,9 @@ (define_insn_and_split "3" [(set (match_operand:VB 0 "register_operand" "=vr") (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr") (match_operand:VB 2 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred (, mode); @@ -227,9 +227,9 @@ (define_insn_and_split "3" (define_insn_and_split "one_cmpl2" [(set (match_operand:VB 0 "register_operand" "=vr") (not:VB (match_operand:VB 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_not (mode); @@ -366,9 +366,9 @@ (define_insn_and_split "2" [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") (any_extend:VWEXTI (match_operand: 1 "register_operand" "vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_vf2 (, mode); @@ -409,9 +409,9 @@ (define_insn_and_split "trunc2" [(set (match_operand: 0 "register_operand" "=vr") (truncate: (match_operand:VWEXTI 1 "register_operand" " vr")))] - "TARGET_VECTOR" + "TARGET_VECTOR && can_create_pseudo_p ()" "#" - "&& can_create_pseudo_p ()" + "&& 1" [(const_int 0)] { insn_code icode = code_for_pred_trunc (mode);