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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id g6-20020a170906594600b0097073f1c48bsi2972681ejr.179.2023.06.12.23.42.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 23:42:27 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=rj1z2wDz; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DA9513858409 for ; Tue, 13 Jun 2023 06:42:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DA9513858409 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686638545; bh=vijDgmsjieFVkHvaWRANvpgSHz9XEjUqsvmodAjjhqQ=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=rj1z2wDzH7GZkzEyGUZgbDk2xH8aY0/RTxt5a5EDDoE3wznmnRtcMu8Bsh9NCUdWb XFHKgkx5sc02Qh9xpojsoH7QCYLSibKNDa5oONg6iJd0AxgYjmLauVGpP0WXkSAK4D YRYFtzMhxQ81eQdYaRLeeC51WPX6W123ziNlheXI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-112.freemail.mail.aliyun.com (out30-112.freemail.mail.aliyun.com [115.124.30.112]) by sourceware.org (Postfix) with ESMTPS id 5CF883858D33 for ; Tue, 13 Jun 2023 06:41:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5CF883858D33 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R681e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046059; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0; TI=SMTPD_---0Vl11Eip_1686638497; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vl11Eip_1686638497) by smtp.aliyun-inc.com; Tue, 13 Jun 2023 14:41:38 +0800 To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, richard.sandiford@arm.com, kito.cheng@gmail.com, christoph.muellner@vrull.eu, jinma.contrib@gmail.com, jimw@sifive.com, Jin Ma Subject: [PATCH] RISC-V: Save and restore FCSR in interrupt functions to avoid program errors. Date: Tue, 13 Jun 2023 14:41:26 +0800 Message-Id: <20230613064126.1323-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Spam-Status: No, score=-19.8 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, URIBL_BLACK, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jin Ma via Gcc-patches From: Jin Ma Reply-To: Jin Ma Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768568701504898272?= X-GMAIL-MSGID: =?utf-8?q?1768568701504898272?= gcc/ChangeLog: * config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR. (riscv_for_each_saved_reg): Save and restore FCSR in interrupt functions. * config/riscv/riscv.md (riscv_frcsr): New patterns. (riscv_fscsr): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/interrupt-fcsr-1.c: New test. * gcc.target/riscv/interrupt-fcsr-2.c: New test. * gcc.target/riscv/interrupt-fcsr-3.c: New test. --- gcc/config/riscv/riscv.cc | 33 ++++++++++++++++++- gcc/config/riscv/riscv.md | 13 ++++++++ .../gcc.target/riscv/interrupt-fcsr-1.c | 14 ++++++++ .../gcc.target/riscv/interrupt-fcsr-2.c | 14 ++++++++ .../gcc.target/riscv/interrupt-fcsr-3.c | 13 ++++++++ 5 files changed, 86 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index de30bf4e567..4ef9692b4db 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4990,7 +4990,8 @@ riscv_compute_frame_info (void) if (cfun->machine->interrupt_handler_p) { HOST_WIDE_INT step1 = riscv_first_stack_step (frame, frame->total_size); - if (! POLY_SMALL_OPERAND_P ((frame->total_size - step1))) + if (! POLY_SMALL_OPERAND_P ((frame->total_size - step1)) + || TARGET_HARD_FLOAT) interrupt_save_prologue_temp = true; } @@ -5035,6 +5036,13 @@ riscv_compute_frame_info (void) frame->save_libcall_adjustment = x_save_size; } + + if (TARGET_HARD_FLOAT + && cfun->machine->interrupt_handler_p + && frame->fmask) + /* In an interrupt function, we need extra space + for the initial saves of FCSR. */ + x_save_size += riscv_stack_align (1 * UNITS_PER_WORD); } /* At the bottom of the frame are any outgoing stack arguments. */ @@ -5282,6 +5290,29 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn, } } + if (regno == RISCV_PROLOGUE_TEMP_REGNUM + && TARGET_HARD_FLOAT + && cfun->machine->interrupt_handler_p + && cfun->machine->frame.fmask) + { + unsigned int fcsr_size = GET_MODE_SIZE (SImode); + if (!epilogue) + { + riscv_save_restore_reg (word_mode, regno, offset, fn); + offset -= fcsr_size; + emit_insn (gen_riscv_frcsr (gen_rtx_REG (SImode, RISCV_PROLOGUE_TEMP_REGNUM))); + riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGNUM, offset, riscv_save_reg); + } + else + { + riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGNUM, offset - fcsr_size, riscv_restore_reg); + emit_insn (gen_riscv_fscsr (gen_rtx_REG (SImode, RISCV_PROLOGUE_TEMP_REGNUM))); + riscv_save_restore_reg (word_mode, regno, offset, fn); + offset -= fcsr_size; + } + continue; + } + riscv_save_restore_reg (word_mode, regno, offset, fn); } diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index d8e935cb934..565e8cd27cd 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -78,6 +78,8 @@ (define_c_enum "unspecv" [ UNSPECV_GPR_RESTORE ;; Floating-point unspecs. + UNSPECV_FRCSR + UNSPECV_FSCSR UNSPECV_FRFLAGS UNSPECV_FSFLAGS UNSPECV_FSNVSNAN @@ -3056,6 +3058,17 @@ (define_insn "gpr_restore_return" "" "") +(define_insn "riscv_frcsr" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec_volatile [(const_int 0)] UNSPECV_FRCSR))] + "TARGET_HARD_FLOAT || TARGET_ZFINX" + "frcsr\t%0") + +(define_insn "riscv_fscsr" + [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSCSR)] + "TARGET_HARD_FLOAT || TARGET_ZFINX" + "fscsr\t%0") + (define_insn "riscv_frflags" [(set (match_operand:SI 0 "register_operand" "=r") (unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))] diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c new file mode 100644 index 00000000000..fe49007c936 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-1.c @@ -0,0 +1,14 @@ +/* Verify that fcsr instructions emitted. */ +/* { dg-do compile } */ +/* { dg-options "" } */ + +extern int foo (void); + +void __attribute__ ((interrupt)) +sub (void) +{ + foo (); +} + +/* { dg-final { scan-assembler-times "frcsr\t" 1 } } */ +/* { dg-final { scan-assembler-times "fscsr\t" 1 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c new file mode 100644 index 00000000000..189d10654e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-2.c @@ -0,0 +1,14 @@ +/* Verify that fcsr instructions emitted. */ +/* { dg-do compile } */ +/* { dg-options "" } */ + +extern int foo (void); +extern float interrupt_count; +void __attribute__ ((interrupt)) +sub (void) +{ + interrupt_count++; +} + +/* { dg-final { scan-assembler-times "frcsr\t" 1 } } */ +/* { dg-final { scan-assembler-times "fscsr\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c new file mode 100644 index 00000000000..28d021c7ae8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-fcsr-3.c @@ -0,0 +1,13 @@ +/* Verify that fcsr instructions are not emitted. */ +/* { dg-do compile } */ +/* { dg-options "" } */ + +extern int foo (void); + +void __attribute__ ((interrupt)) +sub (void) +{ +} + +/* { dg-final { scan-assembler-not "frcsr\t" } } */ +/* { dg-final { scan-assembler-not "fscsr\t" } } */