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[8.43.85.97]) by mx.google.com with ESMTPS id n5-20020aa7db45000000b00514be2f2355si5599408edt.109.2023.06.12.01.09.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 01:09:31 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=uvL88j+I; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 68FC93858C5E for ; Mon, 12 Jun 2023 08:09:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 68FC93858C5E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1686557370; bh=UIsA55cAijKLCV8IKwi5VbfBpSx4XgtWqV4zZgSWalw=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=uvL88j+ILenQro41x0iajhLcGr7fgqzWk9olzoNxEK9O8BqfoY7SZrf7eVoOldmaE HzVkMTSDx/S4/5TZGJ0XaE6NYp46NL5wPrNYnnpPx9XqCUtnUAr54Dt3H0yAQ8d9Uj 6X07/Gp8Kb6y8MnwjuO/wFpqUkvVU9dogsQk6SLI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 1410A3858D28 for ; Mon, 12 Jun 2023 08:08:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1410A3858D28 X-IronPort-AV: E=McAfee;i="6600,9927,10738"; a="355470003" X-IronPort-AV: E=Sophos;i="6.00,236,1681196400"; d="scan'208";a="355470003" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2023 01:08:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10738"; a="661493422" X-IronPort-AV: E=Sophos;i="6.00,236,1681196400"; d="scan'208";a="661493422" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga003.jf.intel.com with ESMTP; 12 Jun 2023 01:08:42 -0700 Received: from yanzhang-dev.sh.intel.com (yanzhang-dev.sh.intel.com [10.239.159.126]) by shvmail02.sh.intel.com (Postfix) with ESMTP id ABE511007BD6; Mon, 12 Jun 2023 16:08:40 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v5] RISC-V: Add vector psabi checking. Date: Mon, 12 Jun 2023 16:08:28 +0800 Message-Id: <20230612080828.1292728-1-yanzhang.wang@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230426123743.3210243-1-yanzhang.wang@intel.com> References: <20230426123743.3210243-1-yanzhang.wang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "yanzhang.wang--- via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: yanzhang.wang@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768203793292577223?= X-GMAIL-MSGID: =?utf-8?q?1768483582594361989?= From: Yanzhang Wang This patch adds support to check function's argument or return is vector type and throw warning if yes. There're two exceptions, - The vector_size attribute. - The intrinsic functions. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set warning flag if func is not builtin * config/riscv/riscv.cc (riscv_scalable_vector_type_p): Determine whether the type is scalable vector. (riscv_arg_has_vector): Determine whether the arg is vector type. (riscv_pass_in_vector_p): Check the vector type param is passed by value. (riscv_init_cumulative_args): The same as header. (riscv_get_arg_info): Add the checking. (riscv_function_value): Check the func return and set warning flag * config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to determine whether warning psabi or not. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Add -Wno-psabi * gcc.target/riscv/vector-abi-1.c: New test. * gcc.target/riscv/vector-abi-2.c: New test. * gcc.target/riscv/vector-abi-3.c: New test. * gcc.target/riscv/vector-abi-4.c: New test. * gcc.target/riscv/vector-abi-5.c: New test. * gcc.target/riscv/vector-abi-6.c: New test. Signed-off-by: Yanzhang Wang Co-authored-by: Kito Cheng --- gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv.cc | 112 +++++++++++++++++- gcc/config/riscv/riscv.h | 5 +- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 +- gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 14 +++ gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 15 +++ gcc/testsuite/gcc.target/riscv/vector-abi-3.c | 14 +++ gcc/testsuite/gcc.target/riscv/vector-abi-4.c | 16 +++ gcc/testsuite/gcc.target/riscv/vector-abi-5.c | 15 +++ gcc/testsuite/gcc.target/riscv/vector-abi-6.c | 20 ++++ 10 files changed, 212 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/vector-abi-6.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 66c1f535d60..90fde5f8be3 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -302,4 +302,6 @@ th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); #endif extern bool riscv_use_divmod_expander (void); +void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int); + #endif /* ! GCC_RISCV_PROTOS_H */ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index de30bf4e567..dd5361c2bd2 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3795,6 +3795,99 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1, GEN_INT (offset2)))); } +/* Use the TYPE_SIZE to distinguish the type with vector_size attribute and + intrinsic vector type. Because we can't get the decl for the params. */ + +static bool +riscv_scalable_vector_type_p (const_tree type) +{ + tree size = TYPE_SIZE (type); + if (size && TREE_CODE (size) == INTEGER_CST) + return false; + + /* For the data type like vint32m1_t, the size code is POLY_INT_CST. */ + return true; +} + +static bool +riscv_arg_has_vector (const_tree type) +{ + bool is_vector = false; + + switch (TREE_CODE (type)) + { + case RECORD_TYPE: + if (!COMPLETE_TYPE_P (type)) + break; + + for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f)) + if (TREE_CODE (f) == FIELD_DECL) + { + tree field_type = TREE_TYPE (f); + if (!TYPE_P (field_type)) + break; + + /* Ignore it if it's fixed length vector. */ + if (VECTOR_TYPE_P (field_type)) + is_vector = riscv_scalable_vector_type_p (field_type); + else + is_vector = riscv_arg_has_vector (field_type); + } + + break; + + case VECTOR_TYPE: + is_vector = riscv_scalable_vector_type_p (type); + break; + + default: + is_vector = false; + break; + } + + return is_vector; +} + +/* Pass the type to check whether it's a vector type or contains vector type. + Only check the value type and no checking for vector pointer type. */ + +static void +riscv_pass_in_vector_p (const_tree type) +{ + static int warned = 0; + + if (type && riscv_arg_has_vector (type) && !warned) + { + warning (OPT_Wpsabi, "ABI for the scalable vector type is currently in " + "experimental stage and may changes in the upcoming version of " + "GCC."); + warned = 1; + } +} + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. */ + +void +riscv_init_cumulative_args (CUMULATIVE_ARGS *cum, + tree fntype ATTRIBUTE_UNUSED, + rtx libname ATTRIBUTE_UNUSED, + tree fndecl, + int caller ATTRIBUTE_UNUSED) +{ + memset (cum, 0, sizeof (*cum)); + + if (fndecl) + { + const tree_function_decl &fn + = FUNCTION_DECL_CHECK (fndecl)->function_decl; + + if (fn.built_in_class == NOT_BUILT_IN) + cum->rvv_psabi_warning = 1; + } +} + /* Fill INFO with information about a single argument, and return an RTL pattern to pass or return the argument. CUM is the cumulative state for earlier arguments. MODE is the mode of this argument and @@ -3816,6 +3909,12 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, info->gpr_offset = cum->num_gprs; info->fpr_offset = cum->num_fprs; + if (cum->rvv_psabi_warning) + { + /* Only check existing of vector type. */ + riscv_pass_in_vector_p (type); + } + /* TODO: Currently, it will cause an ICE for --param riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here let GCC generate loads/stores. Ideally, we should either warn the user not @@ -3973,7 +4072,18 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode) } memset (&args, 0, sizeof args); - return riscv_get_arg_info (&info, &args, mode, type, true, true); + + const_tree arg_type = type; + if (func && DECL_RESULT (func)) + { + const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl; + if (fn.built_in_class == NOT_BUILT_IN) + args.rvv_psabi_warning = 1; + + arg_type = TREE_TYPE (DECL_RESULT (func)); + } + + return riscv_get_arg_info (&info, &args, mode, arg_type, true, true); } /* Implement TARGET_PASS_BY_REFERENCE. */ diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 4541255a8ae..bfd9b7551bc 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -677,6 +677,8 @@ typedef struct { /* Number of floating-point registers used so far, likewise. */ unsigned int num_fprs; + + int rvv_psabi_warning; } CUMULATIVE_ARGS; /* Initialize a variable CUM of type CUMULATIVE_ARGS @@ -684,7 +686,8 @@ typedef struct { For a library call, FNTYPE is 0. */ #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ - memset (&(CUM), 0, sizeof (CUM)) + riscv_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT), \ + (N_NAMED_ARGS) != -1) #define EPILOGUE_USES(REGNO) riscv_epilogue_uses (REGNO) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 5e69235a268..ad79d0e9a8d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -43,7 +43,7 @@ dg-init # Main loop. set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ - "" $CFLAGS + "-Wno-psabi" $CFLAGS gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ "" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c new file mode 100644 index 00000000000..969f14277a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +void +fun (vint32m1_t a) { } /* { dg-warning "the scalable vector type" } */ + +void +bar () +{ + vint32m1_t a; + fun (a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c new file mode 100644 index 00000000000..63d97d30fc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ + +#include "riscv_vector.h" + +vint32m1_t +fun (vint32m1_t* a) { return *a; } /* { dg-warning "the scalable vector type" } */ + +void +bar () +{ + vint32m1_t a; + fun (&a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c new file mode 100644 index 00000000000..90ece60cc6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +vint32m1_t* +fun (vint32m1_t* a) { return a; } /* { dg-bogus "the scalable vector type" } */ + +void +bar () +{ + vint32m1_t a; + fun (&a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c new file mode 100644 index 00000000000..ecf6d4cc26b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-4.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +typedef int v4si __attribute__ ((vector_size (16))); + +v4si +fun (v4si a) { return a; } /* { dg-bogus "the scalable vector type" } */ + +void +bar () +{ + v4si a; + fun (a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c new file mode 100644 index 00000000000..6053e0783b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-5.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +typedef int v4si __attribute__ ((vector_size (16))); +struct A { int a; v4si b; }; + +void +fun (struct A a) {} /* { dg-bogus "the scalable vector type" } */ + +void +bar () +{ + struct A a; + fun (a); +} diff --git a/gcc/testsuite/gcc.target/riscv/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c new file mode 100644 index 00000000000..63bc4a89805 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/vector-abi-6.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ +#include "riscv_vector.h" + +void +foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, + size_t n, int cond) { + size_t vl; + if (cond) + vl = __riscv_vsetvlmax_e32m1(); + else + vl = __riscv_vsetvlmax_e16mf2(); + for (size_t i = 0; i < n; i += 1) + { + vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the scalable vector type" } */ + vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl); + vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl); + __riscv_vse32_v_i32m1(out, c, vl); + } +}