diff mbox series

[v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern

Message ID 20230606123646.1553843-1-pan2.li@intel.com
State Unresolved
Headers
Series [v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern |

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Commit Message

Li, Pan2 via Gcc-patches June 6, 2023, 12:36 p.m. UTC 
  From: Pan Li <pan2.li@intel.com>

This patch would like to refactor the ZVFHMIN implementation by
separated iterator and pattern. Thus, we can tell the sub extension
between the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/vector-iterators.md: Move ZVFHMIN related
	items to separated iterators.
	* config/riscv/vector.md (@pred_extend<mode>): New pattern for
	the ZVFHMIN instruction.
	(@pred_trunc<mode>): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
 gcc/config/riscv/vector-iterators.md          | 28 ++++++++-----
 gcc/config/riscv/vector.md                    | 40 +++++++++++++++++++
 .../riscv/rvv/base/zvfh-over-zvfhmin.c        | 25 ++++++++++++
 3 files changed, 83 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

Comments

juzhe.zhong@rivai.ai June 6, 2023, 2:07 p.m. UTC | #1 
+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])

why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?




juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-06-06 20:36
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li <pan2.li@intel.com>
 
This patch would like to refactor the ZVFHMIN implementation by
separated iterator and pattern. Thus, we can tell the sub extension
between the ZVFHMIN and ZVFH.
 
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
 
gcc/ChangeLog:
 
* config/riscv/vector-iterators.md: Move ZVFHMIN related
items to separated iterators.
* config/riscv/vector.md (@pred_extend<mode>): New pattern for
the ZVFHMIN instruction.
(@pred_trunc<mode>): Likewise.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md          | 28 ++++++++-----
gcc/config/riscv/vector.md                    | 40 +++++++++++++++++++
.../riscv/rvv/base/zvfh-over-zvfhmin.c        | 25 ++++++++++++
3 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
 
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
   (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
   (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
   (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
   (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
   (VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
   (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
   (VNx16DI "VNx16SI")
-
-  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
   (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
   (VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+  (VNx1SF "VNx1HF")
+  (VNx2SF "VNx2HF")
+  (VNx4SF "VNx4HF")
+  (VNx8SF "VNx8HF")
+  (VNx16SF "VNx16HF")
+  (VNx32SF "VNx32HF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
   (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
   (VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
@@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [
   (VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
   (VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
   (VNx16DI "vnx16si")
-  (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
   (VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
   (VNx16DF "vnx16sf")
])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..b498669b874 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7124,6 +7124,25 @@ (define_insn "@pred_extend<mode>"
   [(set_attr "type" "vfwcvtftof")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_extend<mode>"
+  [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand"       "=&vr,  &vr")
+ (if_then_else:V_ZVFHMIN_SF
+   (unspec:<VM>
+     [(match_operand:<VM> 1 "vector_mask_operand"       "vmWc1,vmWc1")
+      (match_operand 4 "vector_length_operand"          "   rK,   rK")
+      (match_operand 5 "const_int_operand"              "    i,    i")
+      (match_operand 6 "const_int_operand"              "    i,    i")
+      (match_operand 7 "const_int_operand"              "    i,    i")
+      (reg:SI VL_REGNUM)
+      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+   (float_extend:V_ZVFHMIN_SF
+      (match_operand:<V_ZVFHMIN> 3 "register_operand"   "   vr,   vr"))
+   (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vfwcvt.f.f.v\t%0,%3%p1"
+  [(set_attr "type" "vfwcvtftof")
+   (set_attr "mode" "<V_ZVFHMIN>")])
+
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
;; -------------------------------------------------------------------------------
@@ -7213,6 +7232,27 @@ (define_insn "@pred_trunc<mode>"
   [(set_attr "type" "vfncvtftof")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_trunc<mode>"
+  [(set (match_operand:<V_ZVFHMIN> 0 "register_operand"       "=vd, vd, vr, vr,  &vr,  &vr")
+ (if_then_else:<V_ZVFHMIN>
+   (unspec:<VM>
+     [(match_operand:<VM> 1 "vector_mask_operand"      " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+      (match_operand 4 "vector_length_operand"         " rK, rK, rK, rK,   rK,   rK")
+      (match_operand 5 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 6 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 7 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 8 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (reg:SI VL_REGNUM)
+      (reg:SI VTYPE_REGNUM)
+      (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+   (float_truncate:<V_ZVFHMIN>
+      (match_operand:V_ZVFHMIN_SF 3 "register_operand" "  0,  0,  0,  0,   vr,   vr"))
+   (match_operand:<V_ZVFHMIN> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
+  "TARGET_VECTOR"
+  "vfncvt.f.f.w\t%0,%3%p1"
+  [(set_attr "type" "vfncvtftof")
+   (set_attr "mode" "<V_ZVFHMIN>")])
+
(define_insn "@pred_rod_trunc<mode>"
   [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand"       "=vd, vd, vr, vr,  &vr,  &vr")
(if_then_else:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
-- 
2.34.1
Li, Pan2 via Gcc-patches June 6, 2023, 2:34 p.m. UTC | #2 
IMO, TARGET_ZVFH || TARGET_ZVFHMIN may be a little readable compares to FP_16, or some context I missed.
Anyway as we discussed offline, will refine this part and add zvfh part in V2.

Pan

From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: Tuesday, June 6, 2023 10:07 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@sifive.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern

+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])

why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?


________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-06 20:36
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

This patch would like to refactor the ZVFHMIN implementation by
separated iterator and pattern. Thus, we can tell the sub extension
between the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Move ZVFHMIN related
items to separated iterators.
* config/riscv/vector.md (@pred_extend<mode>): New pattern for
the ZVFHMIN instruction.
(@pred_trunc<mode>): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md          | 28 ++++++++-----
gcc/config/riscv/vector.md                    | 40 +++++++++++++++++++
.../riscv/rvv/base/zvfh-over-zvfhmin.c        | 25 ++++++++++++
3 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
   (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
   (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
   (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
   (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
   (VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
   (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
   (VNx16DI "VNx16SI")
-
-  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
   (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
   (VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+  (VNx1SF "VNx1HF")
+  (VNx2SF "VNx2HF")
+  (VNx4SF "VNx4HF")
+  (VNx8SF "VNx8HF")
+  (VNx16SF "VNx16HF")
+  (VNx32SF "VNx32HF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
   (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
   (VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
@@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [
   (VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
   (VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
   (VNx16DI "vnx16si")
-  (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
   (VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
   (VNx16DF "vnx16sf")
])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..b498669b874 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7124,6 +7124,25 @@ (define_insn "@pred_extend<mode>"
   [(set_attr "type" "vfwcvtftof")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_extend<mode>"
+  [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand"       "=&vr,  &vr")
+ (if_then_else:V_ZVFHMIN_SF
+   (unspec:<VM>
+     [(match_operand:<VM> 1 "vector_mask_operand"       "vmWc1,vmWc1")
+      (match_operand 4 "vector_length_operand"          "   rK,   rK")
+      (match_operand 5 "const_int_operand"              "    i,    i")
+      (match_operand 6 "const_int_operand"              "    i,    i")
+      (match_operand 7 "const_int_operand"              "    i,    i")
+      (reg:SI VL_REGNUM)
+      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+   (float_extend:V_ZVFHMIN_SF
+      (match_operand:<V_ZVFHMIN> 3 "register_operand"   "   vr,   vr"))
+   (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vfwcvt.f.f.v\t%0,%3%p1"
+  [(set_attr "type" "vfwcvtftof")
+   (set_attr "mode" "<V_ZVFHMIN>")])
+
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
;; -------------------------------------------------------------------------------
@@ -7213,6 +7232,27 @@ (define_insn "@pred_trunc<mode>"
   [(set_attr "type" "vfncvtftof")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_trunc<mode>"
+  [(set (match_operand:<V_ZVFHMIN> 0 "register_operand"       "=vd, vd, vr, vr,  &vr,  &vr")
+ (if_then_else:<V_ZVFHMIN>
+   (unspec:<VM>
+     [(match_operand:<VM> 1 "vector_mask_operand"      " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+      (match_operand 4 "vector_length_operand"         " rK, rK, rK, rK,   rK,   rK")
+      (match_operand 5 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 6 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 7 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 8 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (reg:SI VL_REGNUM)
+      (reg:SI VTYPE_REGNUM)
+      (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+   (float_truncate:<V_ZVFHMIN>
+      (match_operand:V_ZVFHMIN_SF 3 "register_operand" "  0,  0,  0,  0,   vr,   vr"))
+   (match_operand:<V_ZVFHMIN> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
+  "TARGET_VECTOR"
+  "vfncvt.f.f.w\t%0,%3%p1"
+  [(set_attr "type" "vfncvtftof")
+   (set_attr "mode" "<V_ZVFHMIN>")])
+
(define_insn "@pred_rod_trunc<mode>"
   [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand"       "=vd, vd, vr, vr,  &vr,  &vr")
(if_then_else:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
Li, Pan2 via Gcc-patches June 6, 2023, 3:34 p.m. UTC | #3 
Update the PATCH V2 as below.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620787.html

Pan

From: Li, Pan2
Sent: Tuesday, June 6, 2023 10:34 PM
To: 钟居哲 <juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern

IMO, TARGET_ZVFH || TARGET_ZVFHMIN may be a little readable compares to FP_16, or some context I missed.
Anyway as we discussed offline, will refine this part and add zvfh part in V2.

Pan

From: 钟居哲 <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Tuesday, June 6, 2023 10:07 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern

+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])

why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?


________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-06 20:36
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

This patch would like to refactor the ZVFHMIN implementation by
separated iterator and pattern. Thus, we can tell the sub extension
between the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.

Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Move ZVFHMIN related
items to separated iterators.
* config/riscv/vector.md (@pred_extend<mode>): New pattern for
the ZVFHMIN instruction.
(@pred_trunc<mode>): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md          | 28 ++++++++-----
gcc/config/riscv/vector.md                    | 40 +++++++++++++++++++
.../riscv/rvv/base/zvfh-over-zvfhmin.c        | 25 ++++++++++++
3 files changed, 83 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
   (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
   (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
   (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
   (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
   (VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
   (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
   (VNx16DI "VNx16SI")
-
-  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
   (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
   (VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+  (VNx1SF "VNx1HF")
+  (VNx2SF "VNx2HF")
+  (VNx4SF "VNx4HF")
+  (VNx8SF "VNx8HF")
+  (VNx16SF "VNx16HF")
+  (VNx32SF "VNx32HF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
   (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
   (VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
@@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [
   (VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
   (VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
   (VNx16DI "vnx16si")
-  (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
   (VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
   (VNx16DF "vnx16sf")
])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..b498669b874 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7124,6 +7124,25 @@ (define_insn "@pred_extend<mode>"
   [(set_attr "type" "vfwcvtftof")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_extend<mode>"
+  [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand"       "=&vr,  &vr")
+ (if_then_else:V_ZVFHMIN_SF
+   (unspec:<VM>
+     [(match_operand:<VM> 1 "vector_mask_operand"       "vmWc1,vmWc1")
+      (match_operand 4 "vector_length_operand"          "   rK,   rK")
+      (match_operand 5 "const_int_operand"              "    i,    i")
+      (match_operand 6 "const_int_operand"              "    i,    i")
+      (match_operand 7 "const_int_operand"              "    i,    i")
+      (reg:SI VL_REGNUM)
+      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+   (float_extend:V_ZVFHMIN_SF
+      (match_operand:<V_ZVFHMIN> 3 "register_operand"   "   vr,   vr"))
+   (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vfwcvt.f.f.v\t%0,%3%p1"
+  [(set_attr "type" "vfwcvtftof")
+   (set_attr "mode" "<V_ZVFHMIN>")])
+
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
;; -------------------------------------------------------------------------------
@@ -7213,6 +7232,27 @@ (define_insn "@pred_trunc<mode>"
   [(set_attr "type" "vfncvtftof")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_trunc<mode>"
+  [(set (match_operand:<V_ZVFHMIN> 0 "register_operand"       "=vd, vd, vr, vr,  &vr,  &vr")
+ (if_then_else:<V_ZVFHMIN>
+   (unspec:<VM>
+     [(match_operand:<VM> 1 "vector_mask_operand"      " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+      (match_operand 4 "vector_length_operand"         " rK, rK, rK, rK,   rK,   rK")
+      (match_operand 5 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 6 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 7 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 8 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (reg:SI VL_REGNUM)
+      (reg:SI VTYPE_REGNUM)
+      (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+   (float_truncate:<V_ZVFHMIN>
+      (match_operand:V_ZVFHMIN_SF 3 "register_operand" "  0,  0,  0,  0,   vr,   vr"))
+   (match_operand:<V_ZVFHMIN> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
+  "TARGET_VECTOR"
+  "vfncvt.f.f.w\t%0,%3%p1"
+  [(set_attr "type" "vfncvtftof")
+   (set_attr "mode" "<V_ZVFHMIN>")])
+
(define_insn "@pred_rod_trunc<mode>"
   [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand"       "=vd, vd, vr, vr,  &vr,  &vr")
(if_then_else:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
Li, Pan2 via Gcc-patches June 7, 2023, 3:02 a.m. UTC | #4 
Update the PATCH v3 with rvv.exp/riscv.exp all passed as below.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620855.html

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Li, Pan2 via Gcc-patches
Sent: Tuesday, June 6, 2023 11:34 PM
To: 钟居哲 <juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern

Update the PATCH V2 as below.

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620787.html

Pan

From: Li, Pan2
Sent: Tuesday, June 6, 2023 10:34 PM
To: 钟居哲 <juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern

IMO, TARGET_ZVFH || TARGET_ZVFHMIN may be a little readable compares to FP_16, or some context I missed.
Anyway as we discussed offline, will refine this part and add zvfh part in V2.

Pan

From: 钟居哲 <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Tuesday, June 6, 2023 10:07 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng <kito.cheng@sifive.com<mailto:kito.cheng@sifive.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>
Subject: Re: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern

+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) 
+&& TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) 
+&& TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) 
+&& TARGET_MIN_VLEN >= 128")
+])

why not just use "TARGET_VECTOR_ELEN_FP_16"
instead of TARGET_ZVFH || TARGET_ZVFHMIN ?


________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-06-06 20:36
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; kito.cheng<mailto:kito.cheng@sifive.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>
Subject: [PATCH v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

This patch would like to refactor the ZVFHMIN implementation by separated iterator and pattern. Thus, we can tell the sub extension between the ZVFHMIN and ZVFH.

Please note the ZVFH will cover the ZVFHMIN instructions. This patch add one test for this.

Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Move ZVFHMIN related items to separated iterators.
* config/riscv/vector.md (@pred_extend<mode>): New pattern for the ZVFHMIN instruction.
(@pred_trunc<mode>): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
gcc/config/riscv/vector-iterators.md          | 28 ++++++++-----
gcc/config/riscv/vector.md                    | 40 +++++++++++++++++++
.../riscv/rvv/base/zvfh-over-zvfhmin.c        | 25 ++++++++++++
3 files changed, 83 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@ (define_mode_iterator VWEXTI [
])
(define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
   (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@ (define_mode_iterator VWEXTF [
   (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
])
+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) 
+&& TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || 
+TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) 
+&& TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) 
+&& TARGET_MIN_VLEN >= 128")
+])
+
(define_mode_iterator VWCONVERTI [
   (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
   (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@ (define_mode_attr V_DOUBLE_TRUNC [
   (VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
   (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
   (VNx16DI "VNx16SI")
-
-  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
   (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
   (VNx16DF "VNx16SF")
])
+(define_mode_attr V_ZVFHMIN [
+  (VNx1SF "VNx1HF")
+  (VNx2SF "VNx2HF")
+  (VNx4SF "VNx4HF")
+  (VNx8SF "VNx8HF")
+  (VNx16SF "VNx16HF")
+  (VNx32SF "VNx32HF")
+])
+
(define_mode_attr V_QUAD_TRUNC [
   (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
   (VNx16SI "VNx16QI") (VNx32SI "VNx32QI") @@ -1201,7 +1210,6 @@ (define_mode_attr v_double_trunc [
   (VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
   (VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
   (VNx16DI "vnx16si")
-  (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
   (VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
   (VNx16DF "vnx16sf")
])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 1d1847bd85a..b498669b874 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7124,6 +7124,25 @@ (define_insn "@pred_extend<mode>"
   [(set_attr "type" "vfwcvtftof")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_extend<mode>"
+  [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand"       "=&vr,  &vr")
+ (if_then_else:V_ZVFHMIN_SF
+   (unspec:<VM>
+     [(match_operand:<VM> 1 "vector_mask_operand"       "vmWc1,vmWc1")
+      (match_operand 4 "vector_length_operand"          "   rK,   rK")
+      (match_operand 5 "const_int_operand"              "    i,    i")
+      (match_operand 6 "const_int_operand"              "    i,    i")
+      (match_operand 7 "const_int_operand"              "    i,    i")
+      (reg:SI VL_REGNUM)
+      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+   (float_extend:V_ZVFHMIN_SF
+      (match_operand:<V_ZVFHMIN> 3 "register_operand"   "   vr,   vr"))
+   (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vfwcvt.f.f.v\t%0,%3%p1"
+  [(set_attr "type" "vfwcvtftof")
+   (set_attr "mode" "<V_ZVFHMIN>")])
+
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions ;; -------------------------------------------------------------------------------
@@ -7213,6 +7232,27 @@ (define_insn "@pred_trunc<mode>"
   [(set_attr "type" "vfncvtftof")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+(define_insn "@pred_trunc<mode>"
+  [(set (match_operand:<V_ZVFHMIN> 0 "register_operand"       "=vd, vd, vr, vr,  &vr,  &vr")
+ (if_then_else:<V_ZVFHMIN>
+   (unspec:<VM>
+     [(match_operand:<VM> 1 "vector_mask_operand"      " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+      (match_operand 4 "vector_length_operand"         " rK, rK, rK, rK,   rK,   rK")
+      (match_operand 5 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 6 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 7 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (match_operand 8 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+      (reg:SI VL_REGNUM)
+      (reg:SI VTYPE_REGNUM)
+      (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+   (float_truncate:<V_ZVFHMIN>
+      (match_operand:V_ZVFHMIN_SF 3 "register_operand" "  0,  0,  0,  0,   vr,   vr"))
+   (match_operand:<V_ZVFHMIN> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
+  "TARGET_VECTOR"
+  "vfncvt.f.f.w\t%0,%3%p1"
+  [(set_attr "type" "vfncvtftof")
+   (set_attr "mode" "<V_ZVFHMIN>")])
+
(define_insn "@pred_rod_trunc<mode>"
   [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand"       "=vd, vd, vr, vr,  &vr,  &vr")
(if_then_else:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16mf4(src, vl); }
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16m4(src, vl); }
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32mf2(src, vl); }
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32m8(src, vl); }
+
+/* { dg-final { scan-assembler-times 
+{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times 
+{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times 
+{vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times 
+{vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */
--
2.34.1
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f4946d84449..986195489f2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -497,13 +497,6 @@  (define_mode_iterator VWEXTI [
 ])
 
 (define_mode_iterator VWEXTF [
-  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
-  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
-  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
-  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
-
   (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128")
   (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
   (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
@@ -511,6 +504,15 @@  (define_mode_iterator VWEXTF [
   (VNx16DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
 ])
 
+(define_mode_iterator V_ZVFHMIN_SF [
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN < 128")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN)")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN > 32")
+  (VNx32SF "TARGET_VECTOR_ELEN_FP_32 && (TARGET_ZVFH || TARGET_ZVFHMIN) && TARGET_MIN_VLEN >= 128")
+])
+
 (define_mode_iterator VWCONVERTI [
   (VNx1SI "TARGET_MIN_VLEN < 128 && TARGET_VECTOR_ELEN_FP_16")
   (VNx2SI "TARGET_VECTOR_ELEN_FP_16")
@@ -1175,12 +1177,19 @@  (define_mode_attr V_DOUBLE_TRUNC [
   (VNx16SI "VNx16HI") (VNx32SI "VNx32HI")
   (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
   (VNx16DI "VNx16SI")
-
-  (VNx1SF "VNx1HF") (VNx2SF "VNx2HF") (VNx4SF "VNx4HF") (VNx8SF "VNx8HF") (VNx16SF "VNx16HF") (VNx32SF "VNx32HF")
   (VNx1DF "VNx1SF") (VNx2DF "VNx2SF") (VNx4DF "VNx4SF") (VNx8DF "VNx8SF")
   (VNx16DF "VNx16SF")
 ])
 
+(define_mode_attr V_ZVFHMIN [
+  (VNx1SF "VNx1HF")
+  (VNx2SF "VNx2HF")
+  (VNx4SF "VNx4HF")
+  (VNx8SF "VNx8HF")
+  (VNx16SF "VNx16HF")
+  (VNx32SF "VNx32HF")
+])
+
 (define_mode_attr V_QUAD_TRUNC [
   (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
   (VNx16SI "VNx16QI") (VNx32SI "VNx32QI")
@@ -1201,7 +1210,6 @@  (define_mode_attr v_double_trunc [
   (VNx16SI "vnx16hi") (VNx32SI "vnx32hi")
   (VNx1DI "vnx1si") (VNx2DI "vnx2si") (VNx4DI "vnx4si") (VNx8DI "vnx8si")
   (VNx16DI "vnx16si")
-  (VNx1SF "vnx1hf") (VNx2SF "vnx2hf") (VNx4SF "vnx4hf") (VNx8SF "vnx8hf") (VNx16SF "vnx16hf") (VNx32SF "vnx32hf")
   (VNx1DF "vnx1sf") (VNx2DF "vnx2sf") (VNx4DF "vnx4sf") (VNx8DF "vnx8sf")
   (VNx16DF "vnx16sf")
 ])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 1d1847bd85a..b498669b874 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7124,6 +7124,25 @@  (define_insn "@pred_extend<mode>"
   [(set_attr "type" "vfwcvtftof")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
+(define_insn "@pred_extend<mode>"
+  [(set (match_operand:V_ZVFHMIN_SF 0 "register_operand"       "=&vr,  &vr")
+	(if_then_else:V_ZVFHMIN_SF
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"       "vmWc1,vmWc1")
+	     (match_operand 4 "vector_length_operand"          "   rK,   rK")
+	     (match_operand 5 "const_int_operand"              "    i,    i")
+	     (match_operand 6 "const_int_operand"              "    i,    i")
+	     (match_operand 7 "const_int_operand"              "    i,    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (float_extend:V_ZVFHMIN_SF
+	     (match_operand:<V_ZVFHMIN> 3 "register_operand"   "   vr,   vr"))
+	  (match_operand:V_ZVFHMIN_SF 2 "vector_merge_operand" "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vfwcvt.f.f.v\t%0,%3%p1"
+  [(set_attr "type" "vfwcvtftof")
+   (set_attr "mode" "<V_ZVFHMIN>")])
+
 ;; -------------------------------------------------------------------------------
 ;; ---- Predicated floating-point narrow conversions
 ;; -------------------------------------------------------------------------------
@@ -7213,6 +7232,27 @@  (define_insn "@pred_trunc<mode>"
   [(set_attr "type" "vfncvtftof")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
+(define_insn "@pred_trunc<mode>"
+  [(set (match_operand:<V_ZVFHMIN> 0 "register_operand"       "=vd, vd, vr, vr,  &vr,  &vr")
+	(if_then_else:<V_ZVFHMIN>
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"      " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
+	     (match_operand 4 "vector_length_operand"         " rK, rK, rK, rK,   rK,   rK")
+	     (match_operand 5 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+	     (match_operand 6 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+	     (match_operand 7 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+	     (match_operand 8 "const_int_operand"             "  i,  i,  i,  i,    i,    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	  (float_truncate:<V_ZVFHMIN>
+	     (match_operand:V_ZVFHMIN_SF 3 "register_operand" "  0,  0,  0,  0,   vr,   vr"))
+	  (match_operand:<V_ZVFHMIN> 2 "vector_merge_operand" " vu,  0, vu,  0,   vu,    0")))]
+  "TARGET_VECTOR"
+  "vfncvt.f.f.w\t%0,%3%p1"
+  [(set_attr "type" "vfncvtftof")
+   (set_attr "mode" "<V_ZVFHMIN>")])
+
 (define_insn "@pred_rod_trunc<mode>"
   [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand"       "=vd, vd, vr, vr,  &vr,  &vr")
 	(if_then_else:<V_DOUBLE_TRUNC>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..32d6657775c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,25 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+  return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+  return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */