diff mbox series

[RISC-V] correct machine mode in save-restore cfi RTL.

Message ID 20230606015723.12297-1-gaofei@eswincomputing.com
State Accepted
Headers
Series [RISC-V] correct machine mode in save-restore cfi RTL. |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Fei Gao June 6, 2023, 1:57 a.m. UTC 
  gcc/ChangeLog:

        * config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): use Pmode for cfi reg/mem machmode
        (riscv_adjust_libcall_cfi_epilogue): use Pmode for cfi reg machmode

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/save-restore-cfi-2.c: New test to check machmode for cfi reg/mem.
---
 gcc/config/riscv/riscv.cc                        |  6 +++---
 .../gcc.target/riscv/save-restore-cfi-2.c        | 16 ++++++++++++++++
 2 files changed, 19 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/save-restore-cfi-2.c

Comments

Jeff Law June 6, 2023, 2:11 a.m. UTC | #1 
On 6/5/23 19:57, Fei Gao wrote:
> gcc/ChangeLog:
> 
>          * config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): use Pmode for cfi reg/mem machmode
>          (riscv_adjust_libcall_cfi_epilogue): use Pmode for cfi reg machmode
> 
> gcc/testsuite/ChangeLog:
> 
>          * gcc.target/riscv/save-restore-cfi-2.c: New test to check machmode for cfi reg/mem.
I rewrapped the ChangeLog to 80 columns and reindented the arguments to 
the gen_frame_mem call to match our formatting guidelines.

Pushed to the trunk.

Thanks,
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index caa7858b864..9eafd281260 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5370,8 +5370,8 @@  riscv_adjust_libcall_cfi_prologue ()
 	else
 	  offset = saved_size - ((regno - S2_REGNUM + 4) * UNITS_PER_WORD);
 
-	reg = gen_rtx_REG (SImode, regno);
-	mem = gen_frame_mem (SImode, plus_constant (Pmode,
+	reg = gen_rtx_REG (Pmode, regno);
+	mem = gen_frame_mem (Pmode, plus_constant (Pmode,
 						    stack_pointer_rtx,
 						    offset));
 
@@ -5510,7 +5510,7 @@  riscv_adjust_libcall_cfi_epilogue ()
   for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
     if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
       {
-	reg = gen_rtx_REG (SImode, regno);
+	reg = gen_rtx_REG (Pmode, regno);
 	dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
       }
 
diff --git a/gcc/testsuite/gcc.target/riscv/save-restore-cfi-2.c b/gcc/testsuite/gcc.target/riscv/save-restore-cfi-2.c
new file mode 100644
index 00000000000..44d805b4de8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/save-restore-cfi-2.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-options "-fdump-rtl-pro_and_epilogue -O2 -march=rv64gc -mabi=lp64d -msave-restore -mcmodel=medany" } */
+/* { dg-skip-if "" { *-*-* } {"-Os" "-O1" "-O0" "-Og" "-O3" "-Oz" "-flto"} } */
+/* { dg-final { scan-rtl-dump {expr_list:REG_CFA_OFFSET \(set \(mem/c:DI} "pro_and_epilogue" } } */
+/* { dg-final { scan-rtl-dump {expr_list:REG_CFA_RESTORE \(reg:DI 8 s0\)} "pro_and_epilogue" } } */
+
+char my_getchar();
+float getf();
+
+int foo()
+{
+  int s0 = my_getchar();
+  float f0 = getf();
+  int b = my_getchar();
+  return f0 + s0 + b;
+}