From patchwork Mon Jun 5 08:18:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Xu X-Patchwork-Id: 103180 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2527066vqr; Mon, 5 Jun 2023 01:19:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ56ZfYo3UfwEzXU2GIqoC8BOpaRW0Ov4FshG+UOzBCzZ8IVdXDSEljNOPsfHsVhHFXAQg2P X-Received: by 2002:a2e:8607:0:b0:2b1:c011:976d with SMTP id a7-20020a2e8607000000b002b1c011976dmr2733281lji.27.1685953145499; Mon, 05 Jun 2023 01:19:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685953145; cv=none; d=google.com; s=arc-20160816; b=VnCBgW1t9XfOVzXOcmE7XP0Fot8niSqvg6015rZV1iNW8hKed+8ZI49fFXdc0ve3n/ gYXCNQXW8axXsQdj/RNlkbx59HZpfC4meP0Ewk2qtWrTGfHXC2jYsqn57cqqq7VqgOvB o9g9hytwvq8nYJyaLN/Cjh1vzSZEyAn0tQU0Y7KO31ccQWYBJNUEjGyDL4wfbN1Ubf7L LvSsTRhw7QiF8kWQtyILFuAQQKs1rsqSciIpXP3p8RWw9zY+wEnff0A78ro7qD9EKOCf hwTYDWg3NT16f/lYJ5PDEehQeGq9ZlTQEmL03xnoyfCK6aSiblzLnakhfRIG7wSLumcD c6mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:message-id:date:subject:cc:to :from:dmarc-filter:delivered-to; bh=hooyapu+QjlXaa39AhWbiNvQxj7G+V+zqS72gXSaI4o=; b=SFaROEz1gH6o/HA5ZP4mBUIowZahnuaUZtdZR8pH6RNoosOThgGb8PfCKIbHfJyM25 UczjJGb51CqfR09ZYq6GsWXy8rkOlQRc0+IuIpa8x6xcWVcXpyp/c0aCcDY4hV9Jldi/ obi5f2k7ezTQv6dkS6geU2v3DavbDM0oDbec2UyomNoGZP56EGM72xEncvcUCPN7s3DN yL69HyDr+Mo8IPwDfnNKJlYCVEcRxA3qd37FTYcOnIYnljdzReF66XZO4FMp/cRMF4Bt HvezKbDUPdn6vxHJ23bgC6KpX2Mbykh4vI2js7uUAv8aV9D7DaUiVpWHCQduY3IrxG8T wGAg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org ([8.43.85.97]) by mx.google.com with ESMTPS id x12-20020aa7d38c000000b0051499c29ecfsi4490149edq.576.2023.06.05.01.19.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 01:19:05 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E541A385C6D0 for ; Mon, 5 Jun 2023 08:19:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from sgoci-sdnproxy-4.icoremail.net (sgoci-sdnproxy-4.icoremail.net [129.150.39.64]) by sourceware.org (Postfix) with ESMTP id D2BC43856634 for ; Mon, 5 Jun 2023 08:18:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D2BC43856634 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id EwgMCgDXdMRQmn1kYQoiAA--.16237S4; Mon, 05 Jun 2023 16:18:24 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai, Li Xu Subject: [PATCH] RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md. Date: Mon, 5 Jun 2023 08:18:22 +0000 Message-Id: <20230605081822.24328-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: EwgMCgDXdMRQmn1kYQoiAA--.16237S4 X-Coremail-Antispam: 1UD129KBjvJXoW3Jw4fKFy7CFyDGr47Gw13XFb_yoWxAw1Dpa ykGF47Xr15trnav343Kr4jqa1DC3W7Jw1UJr47AwsrAa48Gw1fJF1vka4Yy34DXFyxZFy7 AF47G3Wa9ayYya7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, MEDICAL_SUBJECT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767850005772601963?= X-GMAIL-MSGID: =?utf-8?q?1767850005772601963?= gcc/ChangeLog: * config/riscv/vector-iterators.md: Fix 'REQUIREMENT' for machine_mode 'MODE'. * config/riscv/vector.md (@pred_indexed_store): change VNX16_QHSI to VNX16_QHSDI. (@pred_indexed_store): Ditto. --- gcc/config/riscv/vector-iterators.md | 26 +++++++++++++------------- gcc/config/riscv/vector.md | 6 +++--- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 90743ed76c5..42cbbb49894 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -148,7 +148,7 @@ ]) (define_mode_iterator VEEWEXT8 [ - (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64") + (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") @@ -188,7 +188,7 @@ (VNx4SF "TARGET_VECTOR_ELEN_FP_32") (VNx8SF "TARGET_VECTOR_ELEN_FP_32") (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") - (VNx1DF "TARGET_VECTOR_ELEN_FP_64") + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_64") (VNx4DF "TARGET_VECTOR_ELEN_FP_64") (VNx8DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") @@ -199,7 +199,7 @@ (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") - (VNx4DI "TARGET_VECTOR_ELEN_64") + (VNx4DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32") @@ -213,11 +213,11 @@ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI VNx4QI VNx8QI (VNx16QI "TARGET_MIN_VLEN >= 128") (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI (VNx8HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI (VNx4SI "TARGET_MIN_VLEN >= 128") - (VNx1DI "TARGET_VECTOR_ELEN_64") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") + (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") - (VNx1DF "TARGET_VECTOR_ELEN_FP_64") + (VNx1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128") (VNx2DF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") ]) @@ -400,26 +400,26 @@ (define_mode_iterator VNX1_QHSDI [ (VNx1QI "TARGET_MIN_VLEN < 128") (VNx1HI "TARGET_MIN_VLEN < 128") (VNx1SI "TARGET_MIN_VLEN < 128") - (VNx1DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx1DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") ]) (define_mode_iterator VNX2_QHSDI [ VNx2QI VNx2HI VNx2SI - (VNx2DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx2DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") ]) (define_mode_iterator VNX4_QHSDI [ VNx4QI VNx4HI VNx4SI - (VNx4DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx4DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") ]) (define_mode_iterator VNX8_QHSDI [ VNx8QI VNx8HI VNx8SI - (VNx8DI "TARGET_64BIT && TARGET_MIN_VLEN > 32") + (VNx8DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64") ]) -(define_mode_iterator VNX16_QHSI [ - VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI "TARGET_MIN_VLEN >= 128") +(define_mode_iterator VNX16_QHSDI [ + VNx16QI VNx16HI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx16DI "TARGET_64BIT && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") ]) (define_mode_iterator VNX32_QHSI [ @@ -435,7 +435,7 @@ (VNx2HI "TARGET_MIN_VLEN == 32") VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32") (VNx64HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") - (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_MIN_VLEN >= 128") + (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128") (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_VECTOR_ELEN_FP_16") @@ -463,7 +463,7 @@ (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN > 32") (VNx4HI "TARGET_MIN_VLEN >= 128") (VNx1HF "TARGET_MIN_VLEN < 128") (VNx2HF "TARGET_MIN_VLEN > 32") (VNx4HF "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SI "TARGET_MIN_VLEN >= 128") - (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") ]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0f6aeac8852..1d1847bd85a 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1669,7 +1669,7 @@ [(set_attr "type" "vstx") (set_attr "mode" "")]) -(define_insn "@pred_indexed_store" +(define_insn "@pred_indexed_store" [(set (mem:BLK (scratch)) (unspec:BLK [(unspec: @@ -1679,10 +1679,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operand 1 "pmode_reg_or_0_operand" " rJ") - (match_operand:VNX16_QHSI 2 "register_operand" " vr") + (match_operand:VNX16_QHSDI 2 "register_operand" " vr") (match_operand:VNX16_QHS 3 "register_operand" " vr")] ORDER))] "TARGET_VECTOR" - "vsxei.v\t%3,(%z1),%2%p0" + "vsxei.v\t%3,(%z1),%2%p0" [(set_attr "type" "vstx") (set_attr "mode" "")])