[NFC] RISC-V: Move optimization patterns into autovec-opt.md

Message ID 20230604093647.4018890-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series [NFC] RISC-V: Move optimization patterns into autovec-opt.md |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai June 4, 2023, 9:36 a.m. UTC
  From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Move all optimization patterns into autovec-opt.md to make organization
easier maintain.

gcc/ChangeLog:

        * config/riscv/autovec-opt.md (*<optab>not<mode>): Move to autovec-opt.md.
        (*n<optab><mode>): Ditto.
        * config/riscv/autovec.md (*<optab>not<mode>): Ditto.
        (*n<optab><mode>): Ditto.
        * config/riscv/vector.md: Ditto.

---
 gcc/config/riscv/autovec-opt.md | 92 +++++++++++++++++++++++++++++++++
 gcc/config/riscv/autovec.md     | 52 -------------------
 gcc/config/riscv/vector.md      | 39 --------------
 3 files changed, 92 insertions(+), 91 deletions(-)
  

Comments

Kito Cheng June 4, 2023, 1:14 p.m. UTC | #1
Lgtm

<juzhe.zhong@rivai.ai>於 2023年6月4日 週日,17:37寫道:

> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Move all optimization patterns into autovec-opt.md to make organization
> easier maintain.
>
> gcc/ChangeLog:
>
>         * config/riscv/autovec-opt.md (*<optab>not<mode>): Move to
> autovec-opt.md.
>         (*n<optab><mode>): Ditto.
>         * config/riscv/autovec.md (*<optab>not<mode>): Ditto.
>         (*n<optab><mode>): Ditto.
>         * config/riscv/vector.md: Ditto.
>
> ---
>  gcc/config/riscv/autovec-opt.md | 92 +++++++++++++++++++++++++++++++++
>  gcc/config/riscv/autovec.md     | 52 -------------------
>  gcc/config/riscv/vector.md      | 39 --------------
>  3 files changed, 92 insertions(+), 91 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec-opt.md
> b/gcc/config/riscv/autovec-opt.md
> index 92cdc4e9a16..f6052b50572 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -78,3 +78,95 @@
>    "vwmulsu.vv\t%0,%3,%4%p1"
>    [(set_attr "type" "viwmul")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> +
> +;;
> -----------------------------------------------------------------------------
> +;; ---- Integer Compare Instructions Simplification
> +;;
> -----------------------------------------------------------------------------
> +;; Simplify OP(V, V) Instructions to VMCLR.m Includes:
> +;; - 1.  VMSNE
> +;; - 2.  VMSLT
> +;; - 3.  VMSLTU
> +;; - 4.  VMSGT
> +;; - 5.  VMSGTU
> +;;
> -----------------------------------------------------------------------------
> +;; Simplify OP(V, V) Instructions to VMSET.m Includes:
> +;; - 1.  VMSEQ
> +;; - 2.  VMSLE
> +;; - 3.  VMSLEU
> +;; - 4.  VMSGE
> +;; - 5.  VMSGEU
> +;;
> -----------------------------------------------------------------------------
> +
> +(define_split
> +  [(set (match_operand:VB      0 "register_operand")
> +       (if_then_else:VB
> +         (unspec:VB
> +           [(match_operand:VB 1 "vector_all_trues_mask_operand")
> +            (match_operand    4 "vector_length_operand")
> +            (match_operand    5 "const_int_operand")
> +            (match_operand    6 "const_int_operand")
> +            (reg:SI VL_REGNUM)
> +            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> +         (match_operand:VB    3 "vector_move_operand")
> +         (match_operand:VB    2 "vector_undef_operand")))]
> +  "TARGET_VECTOR"
> +  [(const_int 0)]
> +  {
> +    emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX
> (<MODE>mode),
> +                            RVV_VUNDEF (<MODE>mode), operands[3],
> +                            operands[4], operands[5]));
> +    DONE;
> +  }
> +)
> +
> +;;
> -------------------------------------------------------------------------
> +;; ---- [BOOL] Binary logical operations (inverted second input)
> +;;
> -------------------------------------------------------------------------
> +;; Includes:
> +;; - vmandnot.mm
> +;; - vmornot.mm
> +;;
> -------------------------------------------------------------------------
> +
> +(define_insn_and_split "*<optab>not<mode>"
> +  [(set (match_operand:VB 0 "register_operand"           "=vr")
> +       (bitmanip_bitwise:VB
> +         (not:VB (match_operand:VB 2 "register_operand" " vr"))
> +         (match_operand:VB 1 "register_operand"         " vr")))]
> +  "TARGET_VECTOR"
> +  "#"
> +  "&& can_create_pseudo_p ()"
> +  [(const_int 0)]
> +  {
> +    insn_code icode = code_for_pred_not (<CODE>, <MODE>mode);
> +    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP,
> operands);
> +    DONE;
> +  }
> +  [(set_attr "type" "vmalu")
> +   (set_attr "mode" "<MODE>")])
> +
> +;;
> -------------------------------------------------------------------------
> +;; ---- [BOOL] Binary logical operations (inverted result)
> +;;
> -------------------------------------------------------------------------
> +;; Includes:
> +;; - vmnand.mm
> +;; - vmnor.mm
> +;; - vmxnor.mm
> +;;
> -------------------------------------------------------------------------
> +
> +(define_insn_and_split "*n<optab><mode>"
> +  [(set (match_operand:VB 0 "register_operand"     "=vr")
> +       (not:VB
> +         (any_bitwise:VB
> +           (match_operand:VB 1 "register_operand" " vr")
> +           (match_operand:VB 2 "register_operand" " vr"))))]
> +  "TARGET_VECTOR"
> +  "#"
> +  "&& can_create_pseudo_p ()"
> +  [(const_int 0)]
> +  {
> +    insn_code icode = code_for_pred_n (<CODE>, <MODE>mode);
> +    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP,
> operands);
> +    DONE;
> +  }
> +  [(set_attr "type" "vmalu")
> +   (set_attr "mode" "<MODE>")])
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index ec038fe87cd..9f4492db23c 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -229,58 +229,6 @@
>    [(set_attr "type" "vmalu")
>     (set_attr "mode" "<MODE>")])
>
> -;;
> -------------------------------------------------------------------------
> -;; ---- [BOOL] Binary logical operations (inverted second input)
> -;;
> -------------------------------------------------------------------------
> -;; Includes:
> -;; - vmandnot.mm
> -;; - vmornot.mm
> -;;
> -------------------------------------------------------------------------
> -
> -(define_insn_and_split "*<optab>not<mode>"
> -  [(set (match_operand:VB 0 "register_operand"           "=vr")
> -       (bitmanip_bitwise:VB
> -         (not:VB (match_operand:VB 2 "register_operand" " vr"))
> -         (match_operand:VB 1 "register_operand"         " vr")))]
> -  "TARGET_VECTOR"
> -  "#"
> -  "&& can_create_pseudo_p ()"
> -  [(const_int 0)]
> -  {
> -    insn_code icode = code_for_pred_not (<CODE>, <MODE>mode);
> -    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP,
> operands);
> -    DONE;
> -  }
> -  [(set_attr "type" "vmalu")
> -   (set_attr "mode" "<MODE>")])
> -
> -;;
> -------------------------------------------------------------------------
> -;; ---- [BOOL] Binary logical operations (inverted result)
> -;;
> -------------------------------------------------------------------------
> -;; Includes:
> -;; - vmnand.mm
> -;; - vmnor.mm
> -;; - vmxnor.mm
> -;;
> -------------------------------------------------------------------------
> -
> -(define_insn_and_split "*n<optab><mode>"
> -  [(set (match_operand:VB 0 "register_operand"     "=vr")
> -       (not:VB
> -         (any_bitwise:VB
> -           (match_operand:VB 1 "register_operand" " vr")
> -           (match_operand:VB 2 "register_operand" " vr"))))]
> -  "TARGET_VECTOR"
> -  "#"
> -  "&& can_create_pseudo_p ()"
> -  [(const_int 0)]
> -  {
> -    insn_code icode = code_for_pred_n (<CODE>, <MODE>mode);
> -    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP,
> operands);
> -    DONE;
> -  }
> -  [(set_attr "type" "vmalu")
> -   (set_attr "mode" "<MODE>")])
> -
>  ;;
> =========================================================================
>  ;; == Comparisons and selects
>  ;;
> =========================================================================
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 2496eff7874..0f6aeac8852 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -8297,44 +8297,5 @@
>    [(set_attr "type" "vssegt<order>x")
>     (set_attr "mode" "<V64T:MODE>")])
>
> -;;
> -----------------------------------------------------------------------------
> -;; ---- Integer Compare Instructions Simplification
> -;;
> -----------------------------------------------------------------------------
> -;; Simplify OP(V, V) Instructions to VMCLR.m Includes:
> -;; - 1.  VMSNE
> -;; - 2.  VMSLT
> -;; - 3.  VMSLTU
> -;; - 4.  VMSGT
> -;; - 5.  VMSGTU
> -;;
> -----------------------------------------------------------------------------
> -;; Simplify OP(V, V) Instructions to VMSET.m Includes:
> -;; - 1.  VMSEQ
> -;; - 2.  VMSLE
> -;; - 3.  VMSLEU
> -;; - 4.  VMSGE
> -;; - 5.  VMSGEU
> -;;
> -----------------------------------------------------------------------------
> -(define_split
> -  [(set (match_operand:VB      0 "register_operand")
> -       (if_then_else:VB
> -         (unspec:VB
> -           [(match_operand:VB 1 "vector_all_trues_mask_operand")
> -            (match_operand    4 "vector_length_operand")
> -            (match_operand    5 "const_int_operand")
> -            (match_operand    6 "const_int_operand")
> -            (reg:SI VL_REGNUM)
> -            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> -         (match_operand:VB    3 "vector_move_operand")
> -         (match_operand:VB    2 "vector_undef_operand")))]
> -  "TARGET_VECTOR"
> -  [(const_int 0)]
> -  {
> -    emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX
> (<MODE>mode),
> -                            RVV_VUNDEF (<MODE>mode), operands[3],
> -                            operands[4], operands[5]));
> -    DONE;
> -  }
> -)
> -
>  (include "autovec.md")
>  (include "autovec-opt.md")
> --
> 2.36.3
>
>
  
Li, Pan2 via Gcc-patches June 4, 2023, 1:37 p.m. UTC | #2
Committed, thanks Kito.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Kito Cheng via Gcc-patches
Sent: Sunday, June 4, 2023 9:14 PM
To: juzhe.zhong@rivai.ai
Cc: gcc-patches@gcc.gnu.org; jeffreyalaw@gmail.com; palmer@rivosinc.com; rdapp.gcc@gmail.com
Subject: Re: [NFC] RISC-V: Move optimization patterns into autovec-opt.md

Lgtm

<juzhe.zhong@rivai.ai>於 2023年6月4日 週日,17:37寫道:

> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Move all optimization patterns into autovec-opt.md to make 
> organization easier maintain.
>
> gcc/ChangeLog:
>
>         * config/riscv/autovec-opt.md (*<optab>not<mode>): Move to 
> autovec-opt.md.
>         (*n<optab><mode>): Ditto.
>         * config/riscv/autovec.md (*<optab>not<mode>): Ditto.
>         (*n<optab><mode>): Ditto.
>         * config/riscv/vector.md: Ditto.
>
> ---
>  gcc/config/riscv/autovec-opt.md | 92 +++++++++++++++++++++++++++++++++
>  gcc/config/riscv/autovec.md     | 52 -------------------
>  gcc/config/riscv/vector.md      | 39 --------------
>  3 files changed, 92 insertions(+), 91 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec-opt.md 
> b/gcc/config/riscv/autovec-opt.md index 92cdc4e9a16..f6052b50572 
> 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -78,3 +78,95 @@
>    "vwmulsu.vv\t%0,%3,%4%p1"
>    [(set_attr "type" "viwmul")
>     (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> +
> +;;
> ----------------------------------------------------------------------
> -------
> +;; ---- Integer Compare Instructions Simplification ;;
> ----------------------------------------------------------------------
> -------
> +;; Simplify OP(V, V) Instructions to VMCLR.m Includes:
> +;; - 1.  VMSNE
> +;; - 2.  VMSLT
> +;; - 3.  VMSLTU
> +;; - 4.  VMSGT
> +;; - 5.  VMSGTU
> +;;
> ----------------------------------------------------------------------
> -------
> +;; Simplify OP(V, V) Instructions to VMSET.m Includes:
> +;; - 1.  VMSEQ
> +;; - 2.  VMSLE
> +;; - 3.  VMSLEU
> +;; - 4.  VMSGE
> +;; - 5.  VMSGEU
> +;;
> ----------------------------------------------------------------------
> -------
> +
> +(define_split
> +  [(set (match_operand:VB      0 "register_operand")
> +       (if_then_else:VB
> +         (unspec:VB
> +           [(match_operand:VB 1 "vector_all_trues_mask_operand")
> +            (match_operand    4 "vector_length_operand")
> +            (match_operand    5 "const_int_operand")
> +            (match_operand    6 "const_int_operand")
> +            (reg:SI VL_REGNUM)
> +            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> +         (match_operand:VB    3 "vector_move_operand")
> +         (match_operand:VB    2 "vector_undef_operand")))]
> +  "TARGET_VECTOR"
> +  [(const_int 0)]
> +  {
> +    emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX
> (<MODE>mode),
> +                            RVV_VUNDEF (<MODE>mode), operands[3],
> +                            operands[4], operands[5]));
> +    DONE;
> +  }
> +)
> +
> +;;
> ----------------------------------------------------------------------
> ---
> +;; ---- [BOOL] Binary logical operations (inverted second input) ;;
> ----------------------------------------------------------------------
> ---
> +;; Includes:
> +;; - vmandnot.mm
> +;; - vmornot.mm
> +;;
> ----------------------------------------------------------------------
> ---
> +
> +(define_insn_and_split "*<optab>not<mode>"
> +  [(set (match_operand:VB 0 "register_operand"           "=vr")
> +       (bitmanip_bitwise:VB
> +         (not:VB (match_operand:VB 2 "register_operand" " vr"))
> +         (match_operand:VB 1 "register_operand"         " vr")))]
> +  "TARGET_VECTOR"
> +  "#"
> +  "&& can_create_pseudo_p ()"
> +  [(const_int 0)]
> +  {
> +    insn_code icode = code_for_pred_not (<CODE>, <MODE>mode);
> +    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP,
> operands);
> +    DONE;
> +  }
> +  [(set_attr "type" "vmalu")
> +   (set_attr "mode" "<MODE>")])
> +
> +;;
> ----------------------------------------------------------------------
> ---
> +;; ---- [BOOL] Binary logical operations (inverted result) ;;
> ----------------------------------------------------------------------
> ---
> +;; Includes:
> +;; - vmnand.mm
> +;; - vmnor.mm
> +;; - vmxnor.mm
> +;;
> ----------------------------------------------------------------------
> ---
> +
> +(define_insn_and_split "*n<optab><mode>"
> +  [(set (match_operand:VB 0 "register_operand"     "=vr")
> +       (not:VB
> +         (any_bitwise:VB
> +           (match_operand:VB 1 "register_operand" " vr")
> +           (match_operand:VB 2 "register_operand" " vr"))))]
> +  "TARGET_VECTOR"
> +  "#"
> +  "&& can_create_pseudo_p ()"
> +  [(const_int 0)]
> +  {
> +    insn_code icode = code_for_pred_n (<CODE>, <MODE>mode);
> +    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP,
> operands);
> +    DONE;
> +  }
> +  [(set_attr "type" "vmalu")
> +   (set_attr "mode" "<MODE>")])
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md 
> index ec038fe87cd..9f4492db23c 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -229,58 +229,6 @@
>    [(set_attr "type" "vmalu")
>     (set_attr "mode" "<MODE>")])
>
> -;;
> ----------------------------------------------------------------------
> --- -;; ---- [BOOL] Binary logical operations (inverted second input) 
> -;;
> ----------------------------------------------------------------------
> ---
> -;; Includes:
> -;; - vmandnot.mm
> -;; - vmornot.mm
> -;;
> ----------------------------------------------------------------------
> ---
> -
> -(define_insn_and_split "*<optab>not<mode>"
> -  [(set (match_operand:VB 0 "register_operand"           "=vr")
> -       (bitmanip_bitwise:VB
> -         (not:VB (match_operand:VB 2 "register_operand" " vr"))
> -         (match_operand:VB 1 "register_operand"         " vr")))]
> -  "TARGET_VECTOR"
> -  "#"
> -  "&& can_create_pseudo_p ()"
> -  [(const_int 0)]
> -  {
> -    insn_code icode = code_for_pred_not (<CODE>, <MODE>mode);
> -    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP,
> operands);
> -    DONE;
> -  }
> -  [(set_attr "type" "vmalu")
> -   (set_attr "mode" "<MODE>")])
> -
> -;;
> ----------------------------------------------------------------------
> --- -;; ---- [BOOL] Binary logical operations (inverted result) -;;
> ----------------------------------------------------------------------
> ---
> -;; Includes:
> -;; - vmnand.mm
> -;; - vmnor.mm
> -;; - vmxnor.mm
> -;;
> ----------------------------------------------------------------------
> ---
> -
> -(define_insn_and_split "*n<optab><mode>"
> -  [(set (match_operand:VB 0 "register_operand"     "=vr")
> -       (not:VB
> -         (any_bitwise:VB
> -           (match_operand:VB 1 "register_operand" " vr")
> -           (match_operand:VB 2 "register_operand" " vr"))))]
> -  "TARGET_VECTOR"
> -  "#"
> -  "&& can_create_pseudo_p ()"
> -  [(const_int 0)]
> -  {
> -    insn_code icode = code_for_pred_n (<CODE>, <MODE>mode);
> -    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP,
> operands);
> -    DONE;
> -  }
> -  [(set_attr "type" "vmalu")
> -   (set_attr "mode" "<MODE>")])
> -
>  ;;
> ======================================================================
> ===
>  ;; == Comparisons and selects
>  ;;
> ======================================================================
> === diff --git a/gcc/config/riscv/vector.md 
> b/gcc/config/riscv/vector.md index 2496eff7874..0f6aeac8852 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -8297,44 +8297,5 @@
>    [(set_attr "type" "vssegt<order>x")
>     (set_attr "mode" "<V64T:MODE>")])
>
> -;;
> ----------------------------------------------------------------------
> ------- -;; ---- Integer Compare Instructions Simplification -;;
> ----------------------------------------------------------------------
> ------- -;; Simplify OP(V, V) Instructions to VMCLR.m Includes:
> -;; - 1.  VMSNE
> -;; - 2.  VMSLT
> -;; - 3.  VMSLTU
> -;; - 4.  VMSGT
> -;; - 5.  VMSGTU
> -;;
> ----------------------------------------------------------------------
> ------- -;; Simplify OP(V, V) Instructions to VMSET.m Includes:
> -;; - 1.  VMSEQ
> -;; - 2.  VMSLE
> -;; - 3.  VMSLEU
> -;; - 4.  VMSGE
> -;; - 5.  VMSGEU
> -;;
> ----------------------------------------------------------------------
> -------
> -(define_split
> -  [(set (match_operand:VB      0 "register_operand")
> -       (if_then_else:VB
> -         (unspec:VB
> -           [(match_operand:VB 1 "vector_all_trues_mask_operand")
> -            (match_operand    4 "vector_length_operand")
> -            (match_operand    5 "const_int_operand")
> -            (match_operand    6 "const_int_operand")
> -            (reg:SI VL_REGNUM)
> -            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> -         (match_operand:VB    3 "vector_move_operand")
> -         (match_operand:VB    2 "vector_undef_operand")))]
> -  "TARGET_VECTOR"
> -  [(const_int 0)]
> -  {
> -    emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX
> (<MODE>mode),
> -                            RVV_VUNDEF (<MODE>mode), operands[3],
> -                            operands[4], operands[5]));
> -    DONE;
> -  }
> -)
> -
>  (include "autovec.md")
>  (include "autovec-opt.md")
> --
> 2.36.3
>
>
  

Patch

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 92cdc4e9a16..f6052b50572 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -78,3 +78,95 @@ 
   "vwmulsu.vv\t%0,%3,%4%p1"
   [(set_attr "type" "viwmul")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+;; -----------------------------------------------------------------------------
+;; ---- Integer Compare Instructions Simplification
+;; -----------------------------------------------------------------------------
+;; Simplify OP(V, V) Instructions to VMCLR.m Includes:
+;; - 1.  VMSNE
+;; - 2.  VMSLT
+;; - 3.  VMSLTU
+;; - 4.  VMSGT
+;; - 5.  VMSGTU
+;; -----------------------------------------------------------------------------
+;; Simplify OP(V, V) Instructions to VMSET.m Includes:
+;; - 1.  VMSEQ
+;; - 2.  VMSLE
+;; - 3.  VMSLEU
+;; - 4.  VMSGE
+;; - 5.  VMSGEU
+;; -----------------------------------------------------------------------------
+
+(define_split
+  [(set (match_operand:VB      0 "register_operand")
+	(if_then_else:VB
+	  (unspec:VB
+	    [(match_operand:VB 1 "vector_all_trues_mask_operand")
+	     (match_operand    4 "vector_length_operand")
+	     (match_operand    5 "const_int_operand")
+	     (match_operand    6 "const_int_operand")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (match_operand:VB    3 "vector_move_operand")
+	  (match_operand:VB    2 "vector_undef_operand")))]
+  "TARGET_VECTOR"
+  [(const_int 0)]
+  {
+    emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX (<MODE>mode),
+			     RVV_VUNDEF (<MODE>mode), operands[3],
+			     operands[4], operands[5]));
+    DONE;
+  }
+)
+
+;; -------------------------------------------------------------------------
+;; ---- [BOOL] Binary logical operations (inverted second input)
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vmandnot.mm
+;; - vmornot.mm
+;; -------------------------------------------------------------------------
+
+(define_insn_and_split "*<optab>not<mode>"
+  [(set (match_operand:VB 0 "register_operand"           "=vr")
+	(bitmanip_bitwise:VB
+	  (not:VB (match_operand:VB 2 "register_operand" " vr"))
+	  (match_operand:VB 1 "register_operand"         " vr")))]
+  "TARGET_VECTOR"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(const_int 0)]
+  {
+    insn_code icode = code_for_pred_not (<CODE>, <MODE>mode);
+    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands);
+    DONE;
+  }
+  [(set_attr "type" "vmalu")
+   (set_attr "mode" "<MODE>")])
+
+;; -------------------------------------------------------------------------
+;; ---- [BOOL] Binary logical operations (inverted result)
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vmnand.mm
+;; - vmnor.mm
+;; - vmxnor.mm
+;; -------------------------------------------------------------------------
+
+(define_insn_and_split "*n<optab><mode>"
+  [(set (match_operand:VB 0 "register_operand"     "=vr")
+	(not:VB
+	  (any_bitwise:VB
+	    (match_operand:VB 1 "register_operand" " vr")
+	    (match_operand:VB 2 "register_operand" " vr"))))]
+  "TARGET_VECTOR"
+  "#"
+  "&& can_create_pseudo_p ()"
+  [(const_int 0)]
+  {
+    insn_code icode = code_for_pred_n (<CODE>, <MODE>mode);
+    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands);
+    DONE;
+  }
+  [(set_attr "type" "vmalu")
+   (set_attr "mode" "<MODE>")])
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index ec038fe87cd..9f4492db23c 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -229,58 +229,6 @@ 
   [(set_attr "type" "vmalu")
    (set_attr "mode" "<MODE>")])
 
-;; -------------------------------------------------------------------------
-;; ---- [BOOL] Binary logical operations (inverted second input)
-;; -------------------------------------------------------------------------
-;; Includes:
-;; - vmandnot.mm
-;; - vmornot.mm
-;; -------------------------------------------------------------------------
-
-(define_insn_and_split "*<optab>not<mode>"
-  [(set (match_operand:VB 0 "register_operand"           "=vr")
-	(bitmanip_bitwise:VB
-	  (not:VB (match_operand:VB 2 "register_operand" " vr"))
-	  (match_operand:VB 1 "register_operand"         " vr")))]
-  "TARGET_VECTOR"
-  "#"
-  "&& can_create_pseudo_p ()"
-  [(const_int 0)]
-  {
-    insn_code icode = code_for_pred_not (<CODE>, <MODE>mode);
-    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands);
-    DONE;
-  }
-  [(set_attr "type" "vmalu")
-   (set_attr "mode" "<MODE>")])
-
-;; -------------------------------------------------------------------------
-;; ---- [BOOL] Binary logical operations (inverted result)
-;; -------------------------------------------------------------------------
-;; Includes:
-;; - vmnand.mm
-;; - vmnor.mm
-;; - vmxnor.mm
-;; -------------------------------------------------------------------------
-
-(define_insn_and_split "*n<optab><mode>"
-  [(set (match_operand:VB 0 "register_operand"     "=vr")
-	(not:VB
-	  (any_bitwise:VB
-	    (match_operand:VB 1 "register_operand" " vr")
-	    (match_operand:VB 2 "register_operand" " vr"))))]
-  "TARGET_VECTOR"
-  "#"
-  "&& can_create_pseudo_p ()"
-  [(const_int 0)]
-  {
-    insn_code icode = code_for_pred_n (<CODE>, <MODE>mode);
-    riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, operands);
-    DONE;
-  }
-  [(set_attr "type" "vmalu")
-   (set_attr "mode" "<MODE>")])
-
 ;; =========================================================================
 ;; == Comparisons and selects
 ;; =========================================================================
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 2496eff7874..0f6aeac8852 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -8297,44 +8297,5 @@ 
   [(set_attr "type" "vssegt<order>x")
    (set_attr "mode" "<V64T:MODE>")])
 
-;; -----------------------------------------------------------------------------
-;; ---- Integer Compare Instructions Simplification
-;; -----------------------------------------------------------------------------
-;; Simplify OP(V, V) Instructions to VMCLR.m Includes:
-;; - 1.  VMSNE
-;; - 2.  VMSLT
-;; - 3.  VMSLTU
-;; - 4.  VMSGT
-;; - 5.  VMSGTU
-;; -----------------------------------------------------------------------------
-;; Simplify OP(V, V) Instructions to VMSET.m Includes:
-;; - 1.  VMSEQ
-;; - 2.  VMSLE
-;; - 3.  VMSLEU
-;; - 4.  VMSGE
-;; - 5.  VMSGEU
-;; -----------------------------------------------------------------------------
-(define_split
-  [(set (match_operand:VB      0 "register_operand")
-	(if_then_else:VB
-	  (unspec:VB
-	    [(match_operand:VB 1 "vector_all_trues_mask_operand")
-	     (match_operand    4 "vector_length_operand")
-	     (match_operand    5 "const_int_operand")
-	     (match_operand    6 "const_int_operand")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (match_operand:VB    3 "vector_move_operand")
-	  (match_operand:VB    2 "vector_undef_operand")))]
-  "TARGET_VECTOR"
-  [(const_int 0)]
-  {
-    emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX (<MODE>mode),
-			     RVV_VUNDEF (<MODE>mode), operands[3],
-			     operands[4], operands[5]));
-    DONE;
-  }
-)
-
 (include "autovec.md")
 (include "autovec-opt.md")