diff mbox series

RISC-V: Remove unnecessary md pattern for TARGET_XTHEADCONDMOV

Message ID 20230602055617.63608-1-lidie@eswincomputing.com
State Accepted
Headers
Series RISC-V: Remove unnecessary md pattern for TARGET_XTHEADCONDMOV |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Die Li June 2, 2023, 5:56 a.m. UTC 
  There are 2 small changes in this patch, but they do not affect the result.

1. Remove unnecessary md pattern for TARGET_XTHEADCONDMOV in thead.md. The operands[4]
in "if_then_else" are always comparison operations, so the generated rtl does not match
the pattern that is expected to be deleted.

2. Change operands[4] from const0_rtx to operands[1] to maintain rtl consistency. Although
when output assembly, only operands[4] CODE will affect the output result.

Signed-off-by: Die Li <lidie@eswincomputing.com>

gcc/ChangeLog:

        * config/riscv/thead.md (*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Delete.
---
 gcc/config/riscv/thead.md | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

Comments

Jeff Law June 3, 2023, 5:03 p.m. UTC | #1 
On 6/1/23 23:56, Die Li wrote:
> There are 2 small changes in this patch, but they do not affect the result.
> 
> 1. Remove unnecessary md pattern for TARGET_XTHEADCONDMOV in thead.md. The operands[4]
> in "if_then_else" are always comparison operations, so the generated rtl does not match
> the pattern that is expected to be deleted.
> 
> 2. Change operands[4] from const0_rtx to operands[1] to maintain rtl consistency. Although
> when output assembly, only operands[4] CODE will affect the output result.
> 
> Signed-off-by: Die Li<lidie@eswincomputing.com>
> 
> gcc/ChangeLog:
> 
>          * config/riscv/thead.md (*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Delete.
Thanks.  I've pushed this to the trunk.
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 0623607d3dc..ea377872bde 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -120,25 +120,12 @@ 
   /* Invert the condition and take else-block.  */
   rtx_code code = GET_CODE (operands[4]);
   code = (code == EQ) ? NE : EQ;
-  operands[4] = gen_rtx_fmt_ee (code, VOIDmode, const0_rtx, const0_rtx);
+  operands[4] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], const0_rtx);
   return "th.mv%C4z\t%0,%z3,%1";
 }
   [(set_attr "type" "condmove")
    (set_attr "mode" "<GPR:MODE>")])
 
-(define_insn "*th_cond_gpr_mov<GPR:mode><GPR2:mode>"
-  [(set (match_operand:GPR 0 "register_operand" "=r,r")
-	(if_then_else:GPR
-	 (match_operand:GPR2 1 "register_operand" "r,r")
-	 (match_operand:GPR 2 "reg_or_0_operand" "rJ,0")
-	 (match_operand:GPR 3 "reg_or_0_operand" "0,rJ")))]
-  "TARGET_XTHEADCONDMOV"
-  "@
-   th.mvnez\t%0,%z2,%1
-   th.mveqz\t%0,%z3,%1"
-  [(set_attr "type" "condmove")
-   (set_attr "mode" "<GPR:MODE>")])
-
 ;; XTheadFmv
 
 ;; In RV32, we lack fmv.x.d and fmv.d.x, but XTheadFmv has instructions