From patchwork Thu Jun 1 07:17:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 101786 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp107778vqr; Thu, 1 Jun 2023 00:18:41 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5jXFs5HhPjhLI4M4Tnh9RVdgrrzXWClIxYfTyymWDRl8IGSzaBO9l6TpTyf9BTnlxXo3KH X-Received: by 2002:a17:907:6d19:b0:962:582d:89bf with SMTP id sa25-20020a1709076d1900b00962582d89bfmr7888663ejc.55.1685603920827; Thu, 01 Jun 2023 00:18:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685603920; cv=none; d=google.com; s=arc-20160816; b=ERgMJoiPmny0wjfnpxcAdiV/sLij5PO5QowrcflFWL30GcJNnTMiW9YWxlwCXwOxPJ YebjL1Ph4D+aiJX0rOorUA4iWoRWh9jIs13nSpUx+Xi/3AH21lnB0Pq0I+CGHyBYddjk q3rSISWtvmQ5Y1VSLy0EUCxqFEg9LgLOHdSYP96ldo9ZwDqLnL83hLZ8uIEPfOj4VkFJ Hi04z5mGRNtJvYnmbLoNpZRtbbWOVB0ZSZDgqIhq8FER2mfKHGaHjmBTMj7LRM6d9BN4 7l7fdIpQHW9Ecng04kd+IlgGiFGhxfj1ux4/fFcbqgH2MWGcE7/ry5JyY4VgGohdA1f5 D0UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=kNyWPw/Unvm7n2SJgvaY2VX6Uur3eKb/4QBLu0CAmTo=; b=mzZB0x0Na+xjW1hqz6piXfCFlyP5MIofTVQx19wECnJpEBG6abr3yjaFj12ytc1NfG Ixxyv2wRXBplgs/QgRZG2OAvDE230S8bz7qmX8x5SXShiAKgcwkuV3SGDYTV8k7kflKP Bze4fxIxAlIMFCALJrmJXHI2blSeri7hcMGS80UaEbc12gGqUY1l18MuqcOzXDstif2l R9gnI2KXrFjEfya7NSRxJdzJitz3oLCNAC5FMxtWdid+5+zeTSUybkgkpp49tyKCPXLZ 2WwujcfEQRH3c8uCsrbg2hFgEQWDKvSwQ3Duq2qIYwQOZ1/J7kWDAAHytqLLW9uFQlPj Yv8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=B+l8BTSy; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id q22-20020a170906145600b0096f87ff31f4si4198360ejc.660.2023.06.01.00.18.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 00:18:40 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=B+l8BTSy; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BF9BD3857C48 for ; Thu, 1 Jun 2023 07:18:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BF9BD3857C48 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685603919; bh=kNyWPw/Unvm7n2SJgvaY2VX6Uur3eKb/4QBLu0CAmTo=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=B+l8BTSynK8B6kmFC0Yn5yCI4VRUfqWFeIs4YOahMrMtYroe0sRxIfKeGi4REBjQH WNvGAF4RumW/936NFUrlBB1m3fzUltfkiU6LHl973OS/sbw8vsWq5Us5oK8rb+W1X5 Muwo7w+iDgM8tmKIP4yjsmrk7UY6PCpBoVjnPQjM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 7E9863858CDB for ; Thu, 1 Jun 2023 07:17:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7E9863858CDB X-IronPort-AV: E=McAfee;i="6600,9927,10727"; a="383744842" X-IronPort-AV: E=Sophos;i="6.00,209,1681196400"; d="scan'208";a="383744842" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jun 2023 00:17:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10727"; a="740266105" X-IronPort-AV: E=Sophos;i="6.00,209,1681196400"; d="scan'208";a="740266105" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga001.jf.intel.com with ESMTP; 01 Jun 2023 00:17:49 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id A590210080CC; Thu, 1 Jun 2023 15:17:48 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: Introduce vfloat16m{f}*_t and their machine mode. Date: Thu, 1 Jun 2023 15:17:46 +0800 Message-Id: <20230601071746.2403557-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767483816945758070?= X-GMAIL-MSGID: =?utf-8?q?1767483816945758070?= From: Pan Li This patch would like to introduce the built-in type vfloat16m{f}*_t, as well as their machine mode VNx*HF. They depend on architecture zvfhmin or zvfh. When givn the zvfhmin or zvfh, the macro TARGET_VECTOR_ELEN_FP_16 will be true. The underlying PATCH will implement the zvfhmin extension based on this. Signed-off-by: Pan Li gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin and zvfh. * config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16. (main): Disable FP16 tuple. * config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro. (TARGET_VECTOR_ELEN_FP_16): Ditto. * config/riscv/riscv-vector-builtins.cc (check_required_extensions): Add FP16. * config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type. (vfloat16mf2_t): Ditto. (vfloat16m1_t): Ditto. (vfloat16m2_t): Ditto. (vfloat16m4_t): Ditto. (vfloat16m8_t): Ditto. * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16): New macro. * config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16 machine mode based on TARGET_VECTOR_ELEN_FP_16. Signed-off-by: Pan Li --- gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/config/riscv/genrvv-type-indexer.cc | 7 +++++-- gcc/config/riscv/riscv-opts.h | 4 ++++ gcc/config/riscv/riscv-vector-builtins.cc | 2 ++ gcc/config/riscv/riscv-vector-builtins.def | 20 +++++++++++++++++++ gcc/config/riscv/riscv-vector-builtins.h | 1 + gcc/config/riscv/riscv-vector-switch.def | 23 ++++++++++++++-------- 7 files changed, 49 insertions(+), 10 deletions(-) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index e6ed3df9ea6..3247d526c0a 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1248,6 +1248,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zve64x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64}, {"zve64f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, {"zve64d", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64}, + {"zvfhmin", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, + {"zvfh", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16}, {"zvl32b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B}, {"zvl64b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B}, diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc index 18e1b375396..8fc93ceaab4 100644 --- a/gcc/config/riscv/genrvv-type-indexer.cc +++ b/gcc/config/riscv/genrvv-type-indexer.cc @@ -54,7 +54,7 @@ valid_type (unsigned sew, int lmul_log2, bool float_p) case 8: return lmul_log2 >= -3 && !float_p; case 16: - return lmul_log2 >= -2 && !float_p; + return lmul_log2 >= -2; case 32: return lmul_log2 >= -1; case 64: @@ -73,6 +73,9 @@ valid_type (unsigned sew, int lmul_log2, unsigned nf, bool float_p) if (nf > 8 || nf < 1) return false; + if (sew == 16 && nf != 1 && float_p) // Disable FP16 tuple in temporarily. + return false; + switch (lmul_log2) { case 1: @@ -342,7 +345,7 @@ main (int argc, const char **argv) fprintf (fp, ")\n"); } // Build for vfloat - for (unsigned sew : {32, 64}) + for (unsigned sew : {16, 32, 64}) for (int lmul_log2 : {-3, -2, -1, 0, 1, 2, 3}) for (unsigned nf : {1, 2, 3, 4, 5, 6, 7, 8}) { diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 5f387d0e393..208a557b8ff 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -154,6 +154,8 @@ enum riscv_entity #define MASK_VECTOR_ELEN_64 (1 << 1) #define MASK_VECTOR_ELEN_FP_32 (1 << 2) #define MASK_VECTOR_ELEN_FP_64 (1 << 3) +/* Align the bit index to riscv-vector-builtins.h. */ +#define MASK_VECTOR_ELEN_FP_16 (1 << 6) #define TARGET_VECTOR_ELEN_32 \ ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0) @@ -163,6 +165,8 @@ enum riscv_entity ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0) #define TARGET_VECTOR_ELEN_FP_64 \ ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0) +#define TARGET_VECTOR_ELEN_FP_16 \ + ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_16) != 0) #define MASK_ZVL32B (1 << 0) #define MASK_ZVL64B (1 << 1) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 9fea70709fd..43bf6d8f262 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -2944,6 +2944,8 @@ check_required_extensions (const function_instance &instance) uint64_t riscv_isa_flags = 0; + if (TARGET_VECTOR_ELEN_FP_16) + riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_16; if (TARGET_VECTOR_ELEN_FP_32) riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_32; if (TARGET_VECTOR_ELEN_FP_64) diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 61346e53d7b..149835f36ac 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -490,6 +490,26 @@ DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, int64, VNx16DI, VNx8DI, VOID, _i6 DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, VNx16DI, VNx8DI, VOID, _u64m8, _u64, _e64m8) +/* Enabled if TARGET_VECTOR_ELEN_FP_16 && 9TARGET_ZVFH or TARGET_ZVFHMIN). */ +/* LMUL = 1/4. */ +DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, VNx2HF, VNx1HF, VOID, + _f16mf4, _f16, _e16mf4) +/* LMUL = 1/2. */ +DEF_RVV_TYPE (vfloat16mf2_t, 18, __rvv_float16mf2_t, float16, VNx4HF, VNx2HF, VNx1HF, + _f16mf2, _f16, _e16mf2) +/* LMUL = 1. */ +DEF_RVV_TYPE (vfloat16m1_t, 17, __rvv_float16m1_t, float16, VNx8HF, VNx4HF, VNx2HF, + _f16m1, _f16, _e16m1) +/* LMUL = 2. */ +DEF_RVV_TYPE (vfloat16m2_t, 17, __rvv_float16m2_t, float16, VNx16HF, VNx8HF, VNx4HF, + _f16m2, _f16, _e16m2) +/* LMUL = 4. */ +DEF_RVV_TYPE (vfloat16m4_t, 17, __rvv_float16m4_t, float16, VNx32HF, VNx16HF, VNx8HF, + _f16m4, _f16, _e16m4) +/* LMUL = 8. */ +DEF_RVV_TYPE (vfloat16m8_t, 16, __rvv_float16m8_t, float16, VNx64HF, VNx32HF, VNx16HF, + _f16m8, _f16, _e16m8) + /* Disable all when !TARGET_VECTOR_ELEN_FP_32. */ /* LMUL = 1/2: Only enble when TARGET_MIN_VLEN > 32. diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 5d434579131..b0c3a42d820 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -108,6 +108,7 @@ static const unsigned int CP_WRITE_CSR = 1U << 5; #define RVV_REQUIRE_ELEN_FP_64 (1 << 3) /* Require FP ELEN >= 64. */ #define RVV_REQUIRE_FULL_V (1 << 4) /* Require Full 'V' extension. */ #define RVV_REQUIRE_MIN_VLEN_64 (1 << 5) /* Require TARGET_MIN_VLEN >= 64. */ +#define RVV_REQUIRE_ELEN_FP_16 (1 << 6) /* Require FP ELEN >= 32. */ /* Enumerates the RVV operand types. */ enum operand_type_index diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index 4b1c32de0a3..52f07709f99 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -120,14 +120,21 @@ ENTRY (VNx4HI, true, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32) ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) ENTRY (VNx1HI, TARGET_MIN_VLEN < 128, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) -/* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported. */ -ENTRY (VNx64HF, false, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_8, 2) -ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2, LMUL_4, 4) -ENTRY (VNx16HF, false, LMUL_8, 2, LMUL_4, 4, LMUL_2, 8) -ENTRY (VNx8HF, false, LMUL_4, 4, LMUL_2, 8, LMUL_1, 16) -ENTRY (VNx4HF, false, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32) -ENTRY (VNx2HF, false, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) -ENTRY (VNx1HF, false, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +/* SEW = 16 for float point. Enabled when 'zvfh' or 'zvfhmin' is given. */ +ENTRY (VNx64HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, \ + LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_8, 2) +ENTRY (VNx32HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, \ + LMUL_RESERVED, 0, LMUL_8, 2, LMUL_4, 4) +ENTRY (VNx16HF, TARGET_VECTOR_ELEN_FP_16, \ + LMUL_8, 2, LMUL_4, 4, LMUL_2, 8) +ENTRY (VNx8HF, TARGET_VECTOR_ELEN_FP_16, \ + LMUL_4, 4, LMUL_2, 8, LMUL_1, 16) +ENTRY (VNx4HF, TARGET_VECTOR_ELEN_FP_16, \ + LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32) +ENTRY (VNx2HF, TARGET_VECTOR_ELEN_FP_16, \ + LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +ENTRY (VNx1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, \ + LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) /* SEW = 32. Disable VNx16SImode when TARGET_MIN_VLEN == 32. For single-precision floating-point, we need TARGET_VECTOR_ELEN_FP_32 to be