diff mbox series

RISC-V: Remove FRM for vfncvt.rod instruction

Message ID 20230531104703.208291-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series RISC-V: Remove FRM for vfncvt.rod instruction |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai May 31, 2023, 10:47 a.m. UTC 
  From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.

gcc/ChangeLog:

        * config/riscv/vector.md: Remove FRM.

---
 gcc/config/riscv/vector.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

Comments

Jeff Law May 31, 2023, 1:02 p.m. UTC | #1 
On 5/31/23 04:47, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Remove FRM.
OK
jeff
Li, Pan2 via Gcc-patches May 31, 2023, 1:51 p.m. UTC | #2 
Committed, thanks Jeff.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches
Sent: Wednesday, May 31, 2023 9:02 PM
To: juzhe.zhong@rivai.ai; gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com; kito.cheng@sifive.com; palmer@dabbelt.com; palmer@rivosinc.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Remove FRM for vfncvt.rod instruction



On 5/31/23 04:47, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Remove FRM.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3c4565dc775..cd41ebbb24f 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7286,10 +7286,8 @@ 
 	     (match_operand 5 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
 	     (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
 	     (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
-	     (match_operand 8 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)
-	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:<V_DOUBLE_TRUNC>
 	    [(float_truncate:<V_DOUBLE_TRUNC>
 	       (match_operand:VWEXTF 3 "register_operand"          "  0,  0,  0,  0,   vr,   vr"))] UNSPEC_ROD)