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[8.43.85.97]) by mx.google.com with ESMTPS id gs12-20020a1709072d0c00b00969d4c425e7si1194097ejc.222.2023.05.30.21.34.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 21:34:36 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=azyOyTdF; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 67F393857713 for ; Wed, 31 May 2023 04:34:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 67F393857713 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685507675; bh=fD6dvP0CcINKJ95PqwoEv0sEjxZGuehq/sfMFP2g0+U=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=azyOyTdFdDgz6Cqo4GpzMUDu6jakkx8uNmDJ2E2u2Gs2ONODSXAE98+oZUoagzip8 ozbwzAWL05ShdyGvYlo0YUcaWxoFHrKQ/Sx2pkNK4cqpUo3oli2hopN86aHTlMK5yU wd5FfX/GFqeWixJD66DdpFuROzOklYkxnRvq+oLs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 4B0253858C5E for ; Wed, 31 May 2023 04:33:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4B0253858C5E Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34ULjZpm019356 for ; Tue, 30 May 2023 21:33:47 -0700 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3qwsb8scv3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 30 May 2023 21:33:47 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 30 May 2023 21:33:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 30 May 2023 21:33:45 -0700 Received: from vpnclient.com (unknown [10.69.242.187]) by maili.marvell.com (Postfix) with ESMTP id 8A7443F7063; Tue, 30 May 2023 21:33:44 -0700 (PDT) To: CC: Andrew Pinski Subject: [PATCH] Fix PR 110042: ifcvt regression due to paradoxical subregs Date: Tue, 30 May 2023 21:32:49 -0700 Message-ID: <20230531043249.2561061-1-apinski@marvell.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: N_0tbG52frinj9AiXPey_4gb4TVDZJn_ X-Proofpoint-GUID: N_0tbG52frinj9AiXPey_4gb4TVDZJn_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-30_18,2023-05-30_01,2023-05-22_02 X-Spam-Status: No, score=-14.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrew Pinski via Gcc-patches From: Andrew Pinski Reply-To: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767382897570176801?= X-GMAIL-MSGID: =?utf-8?q?1767382897570176801?= After r14-1014-gc5df248509b489364c573e8, GCC started to emit directly a zero_extract for `(t1&0x8)!=0`. This introduced a small regression where ifcvt would not do the ifconversion as there is now a paradoxical subreg in the dest which was being rejected. Since paradoxical subreg set the whole register, we can treat it as the same as a reg in the two places. OK? Bootstrapped and tested on x86_64-linux-gnu and aarch64-linux-gnu. gcc/ChangeLog: PR rtl-optimization/110042 * ifcvt.cc (bbs_ok_for_cmove_arith): Allow paradoxical subregs. (bb_valid_for_noce_process_p): Strip the subreg for the SET_DEST. gcc/testsuite/ChangeLog: PR rtl-optimization/110042 * gcc.target/aarch64/csel_bfx_2.c: New test. --- gcc/ifcvt.cc | 14 ++++++---- gcc/testsuite/gcc.target/aarch64/csel_bfx_2.c | 27 +++++++++++++++++++ 2 files changed, 36 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/csel_bfx_2.c diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index 868eda93251..0b180b4568f 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -2022,7 +2022,7 @@ bbs_ok_for_cmove_arith (basic_block bb_a, basic_block bb_b, rtx to_rename) } /* Make sure this is a REG and not some instance - of ZERO_EXTRACT or SUBREG or other dangerous stuff. + of ZERO_EXTRACT or non-paradoxical SUBREG or other dangerous stuff. If we have a memory destination then we have a pair of simple basic blocks performing an operation of the form [addr] = c ? a : b. bb_valid_for_noce_process_p will have ensured that these are @@ -2030,7 +2030,8 @@ bbs_ok_for_cmove_arith (basic_block bb_a, basic_block bb_b, rtx to_rename) to be renamed. Assert that the callers set this up properly. */ if (MEM_P (SET_DEST (sset_b))) gcc_assert (rtx_equal_p (SET_DEST (sset_b), to_rename)); - else if (!REG_P (SET_DEST (sset_b))) + else if (!REG_P (SET_DEST (sset_b)) + && !paradoxical_subreg_p (SET_DEST (sset_b))) { BITMAP_FREE (bba_sets); return false; @@ -3136,14 +3137,17 @@ bb_valid_for_noce_process_p (basic_block test_bb, rtx cond, rtx sset = single_set (insn); gcc_assert (sset); + rtx dest = SET_DEST (sset); + if (SUBREG_P (dest)) + dest = SUBREG_REG (dest); if (contains_mem_rtx_p (SET_SRC (sset)) - || !REG_P (SET_DEST (sset)) - || reg_overlap_mentioned_p (SET_DEST (sset), cond)) + || !REG_P (dest) + || reg_overlap_mentioned_p (dest, cond)) goto free_bitmap_and_fail; potential_cost += pattern_cost (sset, speed_p); - bitmap_set_bit (test_bb_temps, REGNO (SET_DEST (sset))); + bitmap_set_bit (test_bb_temps, REGNO (dest)); } } diff --git a/gcc/testsuite/gcc.target/aarch64/csel_bfx_2.c b/gcc/testsuite/gcc.target/aarch64/csel_bfx_2.c new file mode 100644 index 00000000000..c3b8a6f45cc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/csel_bfx_2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +unsigned +f1(int t, int t1) +{ + int tt = 0; + if(t) + tt = (t1&0x8)!=0; + return tt; +} +struct f +{ + unsigned t:3; + unsigned t1:4; +}; +unsigned +f2(int t, struct f y) +{ + int tt = 0; + if(t) + tt = y.t1; + return tt; +} +/* Both f1 and f2 should produce a csel and not a cbz on the argument. */ +/* { dg-final { scan-assembler-times "csel\t" 2 } } */ +/* { dg-final { scan-assembler-times "ubfx\t" 2 } } */ +/* { dg-final { scan-assembler-not "cbz\t" } } */