diff mbox series

[V2] RISC-V: Fix warning in riscv.md

Message ID 20230530020821.877778-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series [V2] RISC-V: Fix warning in riscv.md |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai May 30, 2023, 2:08 a.m. UTC 
  From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Notice there is warning:
../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md: In function ‘rtx_def* gen_anddi3(rtx, rtx, rtx)’:
../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))

Add unsigned conversion to fix this warning.

gcc/ChangeLog:

        * config/riscv/riscv.md: Fix signed and unsigned comparison warning.

---
 gcc/config/riscv/riscv.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Kito Cheng May 30, 2023, 2:09 a.m. UTC | #1 
LGTM :)

On Tue, May 30, 2023 at 10:09 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Notice there is warning:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
>        if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
>        else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md: In function ‘rtx_def* gen_anddi3(rtx, rtx, rtx)’:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
>        if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
>        else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
>
> Add unsigned conversion to fix this warning.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.md: Fix signed and unsigned comparison warning.
>
> ---
>  gcc/config/riscv/riscv.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index aba203318a7..f545874edc1 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1353,9 +1353,9 @@
>    if (CONST_INT_P (operands[2]))
>      {
>        enum machine_mode tmode = VOIDmode;
> -      if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> +      if (UINTVAL (operands[2]) == GET_MODE_MASK (HImode))
>         tmode = HImode;
> -      else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> +      else if (UINTVAL (operands[2]) == GET_MODE_MASK (SImode))
>         tmode = SImode;
>
>        if (tmode != VOIDmode)
> --
> 2.36.3
>
Li, Pan2 via Gcc-patches May 30, 2023, 2:17 a.m. UTC | #2 
Committed, thanks Kito.

Pan

-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Kito Cheng via Gcc-patches
Sent: Tuesday, May 30, 2023 10:10 AM
To: juzhe.zhong@rivai.ai
Cc: gcc-patches@gcc.gnu.org; kito.cheng@sifive.com; palmer@dabbelt.com; palmer@rivosinc.com; jeffreyalaw@gmail.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH V2] RISC-V: Fix warning in riscv.md

LGTM :)

On Tue, May 30, 2023 at 10:09 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Notice there is warning:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
>        if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
>        else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md: In function ‘rtx_def* gen_anddi3(rtx, rtx, rtx)’:
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
>        if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> ../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
>        else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
>
> Add unsigned conversion to fix this warning.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.md: Fix signed and unsigned comparison warning.
>
> ---
>  gcc/config/riscv/riscv.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md 
> index aba203318a7..f545874edc1 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1353,9 +1353,9 @@
>    if (CONST_INT_P (operands[2]))
>      {
>        enum machine_mode tmode = VOIDmode;
> -      if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
> +      if (UINTVAL (operands[2]) == GET_MODE_MASK (HImode))
>         tmode = HImode;
> -      else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
> +      else if (UINTVAL (operands[2]) == GET_MODE_MASK (SImode))
>         tmode = SImode;
>
>        if (tmode != VOIDmode)
> --
> 2.36.3
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index aba203318a7..f545874edc1 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1353,9 +1353,9 @@ 
   if (CONST_INT_P (operands[2]))
     {
       enum machine_mode tmode = VOIDmode;
-      if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
+      if (UINTVAL (operands[2]) == GET_MODE_MASK (HImode))
 	tmode = HImode;
-      else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
+      else if (UINTVAL (operands[2]) == GET_MODE_MASK (SImode))
 	tmode = SImode;
 
       if (tmode != VOIDmode)