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[8.43.85.97]) by mx.google.com with ESMTPS id rl21-20020a170907217500b0094f4f2ba2b8si3983479ejb.274.2023.05.28.23.51.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 May 2023 23:51:40 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 65685385701B for ; Mon, 29 May 2023 06:51:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18]) by sourceware.org (Postfix) with ESMTPS id B6CCE3858D32 for ; Mon, 29 May 2023 06:51:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B6CCE3858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp66t1685343059tph5wcxe Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 29 May 2023 14:50:58 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: eeGIu46hDGhwsfDR0osQ8Exv699iT/f6kFe0ijW8Q1KTxlKHJw8UZ8n4BK9oh 1/kV1Bz89bd0gh87jsS+lo0lm4syChivbG6Sn9gWh+fD5YoQQyM0FGJQ0sU/NXUGwl+uRMP 1jJhmkf+sflVLcdVjDXwF94X1mGGfSfCehVi9VNGBQFaR3IOQWW+83bPUE7WjEcpOJ/s05o cRmyXDGIEEmTr8G8r68hY4+MNFl2IPFIIVdr1PxLGm56jebFtTOX94+headCOH5R5syPsXR jmyPw8EhlobQ5Vry4wzCsEvyOj+Flk4OerMZ0eSn4Z+rdBxrXEy0X6qRC7MjHsbyHnArZhc YiBicJK/x2e8aqp5z/FgVoQC03MPDsTLNlr1h1OVCeTqaEDV9HXg7Ufchf94eZv+1ge2QpD 2FKQS7AgM8E= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5931725277954640257 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add RVV FNMA auto-vectorization support Date: Mon, 29 May 2023 14:50:56 +0800 Message-Id: <20230529065056.199188-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1767210327291977901?= X-GMAIL-MSGID: =?utf-8?q?1767210327291977901?= From: Juzhe-Zhong Like FMA, Add FNMA auto-vectorization support. gcc/ChangeLog: * config/riscv/autovec.md (fnma4): New pattern. (*fnma): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test. * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test. * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test. * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test. --- gcc/config/riscv/autovec.md | 45 ++++++++ .../riscv/rvv/autovec/ternop/ternop-4.c | 28 +++++ .../riscv/rvv/autovec/ternop/ternop-5.c | 34 ++++++ .../riscv/rvv/autovec/ternop/ternop-6.c | 33 ++++++ .../riscv/rvv/autovec/ternop/ternop_run-4.c | 84 ++++++++++++++ .../riscv/rvv/autovec/ternop/ternop_run-5.c | 104 ++++++++++++++++++ .../riscv/rvv/autovec/ternop/ternop_run-6.c | 104 ++++++++++++++++++ 7 files changed, 432 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index eff3e484fb4..20004a8af27 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -606,3 +606,48 @@ } [(set_attr "type" "vimuladd") (set_attr "mode" "")]) + +;; ------------------------------------------------------------------------- +;; ---- [INT] VMACC and VMADD +;; ------------------------------------------------------------------------- +;; Includes: +;; - vnmsac +;; - vnmsub +;; ------------------------------------------------------------------------- + +(define_expand "fnma4" + [(parallel + [(set (match_operand:VI 0 "register_operand" "=vr") + (minus:VI + (match_operand:VI 3 "register_operand" " vr") + (mult:VI + (match_operand:VI 1 "register_operand" " vr") + (match_operand:VI 2 "register_operand" " vr")))) + (clobber (match_scratch:SI 4))])] + "TARGET_VECTOR" + {}) + +(define_insn_and_split "*fnma" + [(set (match_operand:VI 0 "register_operand" "=vr, vr, ?&vr") + (minus:VI + (match_operand:VI 3 "register_operand" " vr, 0, vr") + (mult:VI + (match_operand:VI 1 "register_operand" " %0, vr, vr") + (match_operand:VI 2 "register_operand" " vr, vr, vr")))) + (clobber (match_scratch:SI 4 "=r,r,r"))] + "TARGET_VECTOR" + "#" + "&& reload_completed" + [(const_int 0)] + { + PUT_MODE (operands[4], Pmode); + riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); + if (which_alternative == 2) + emit_insn (gen_rtx_SET (operands[0], operands[3])); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]}; + riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (mode), + riscv_vector::RVV_TERNOP, ops, operands[4]); + DONE; + } + [(set_attr "type" "vimuladd") + (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c new file mode 100644 index 00000000000..22d11de89a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ + +#include + +#define TEST_TYPE(TYPE) \ + __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst, \ + TYPE *__restrict a, \ + TYPE *__restrict b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] += -(a[i] * b[i]); \ + } + +#define TEST_ALL() \ + TEST_TYPE (int8_t) \ + TEST_TYPE (uint8_t) \ + TEST_TYPE (int16_t) \ + TEST_TYPE (uint16_t) \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvnmsub\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c new file mode 100644 index 00000000000..6d5cf0a4da3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ + +#include + +#define TEST_TYPE(TYPE) \ + __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dest1, \ + TYPE *__restrict dest2, \ + TYPE *__restrict dest3, \ + TYPE *__restrict src1, \ + TYPE *__restrict src2, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + dest1[i] += -(src1[i] * src2[i]); \ + dest2[i] += src1[i] * dest1[i]; \ + dest3[i] += src2[i] * dest2[i]; \ + } \ + } + +#define TEST_ALL() \ + TEST_TYPE (int8_t) \ + TEST_TYPE (uint8_t) \ + TEST_TYPE (int16_t) \ + TEST_TYPE (uint16_t) \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvnmsac\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c new file mode 100644 index 00000000000..a2186e67222 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */ + +#include + +#define TEST_TYPE(TYPE) \ + __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dest1, \ + TYPE *__restrict dest2, \ + TYPE *__restrict dest3, \ + TYPE *__restrict src1, \ + TYPE *__restrict src2, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + { \ + dest1[i] = -(src1[i] * src2[i]) + dest2[i]; \ + dest2[i] += src1[i] * dest1[i]; \ + dest3[i] += src2[i] * dest2[i]; \ + } \ + } + +#define TEST_ALL() \ + TEST_TYPE (int8_t) \ + TEST_TYPE (uint8_t) \ + TEST_TYPE (int16_t) \ + TEST_TYPE (uint16_t) \ + TEST_TYPE (int32_t) \ + TEST_TYPE (uint32_t) \ + TEST_TYPE (int64_t) \ + TEST_TYPE (uint64_t) + +TEST_ALL () + +/* { dg-final { scan-assembler-times {\tvmv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c new file mode 100644 index 00000000000..379ab259816 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c @@ -0,0 +1,84 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ + +#include "ternop-4.c" + +#define TEST_LOOP(TYPE, NUM) \ + { \ + TYPE array1_##NUM[NUM] = {}; \ + TYPE array2_##NUM[NUM] = {}; \ + TYPE array3_##NUM[NUM] = {}; \ + TYPE array4_##NUM[NUM] = {}; \ + for (int i = 0; i < NUM; ++i) \ + { \ + array1_##NUM[i] = (i & 1) + 5; \ + array2_##NUM[i] = i - NUM / 3; \ + array3_##NUM[i] = NUM - NUM / 3 - i; \ + array4_##NUM[i] = NUM - NUM / 3 - i; \ + asm volatile("" ::: "memory"); \ + } \ + ternop_##TYPE (array3_##NUM, array1_##NUM, array2_##NUM, NUM); \ + for (int i = 0; i < NUM; i++) \ + if (array3_##NUM[i] \ + != (TYPE) (-(array1_##NUM[i] * array2_##NUM[i]) + array4_##NUM[i])) \ + __builtin_abort (); \ + } + +int __attribute__ ((optimize (0))) main () +{ + TEST_LOOP (int8_t, 7) + TEST_LOOP (uint8_t, 7) + TEST_LOOP (int16_t, 7) + TEST_LOOP (uint16_t, 7) + TEST_LOOP (int32_t, 7) + TEST_LOOP (uint32_t, 7) + TEST_LOOP (int64_t, 7) + TEST_LOOP (uint64_t, 7) + + TEST_LOOP (int8_t, 16) + TEST_LOOP (uint8_t, 16) + TEST_LOOP (int16_t, 16) + TEST_LOOP (uint16_t, 16) + TEST_LOOP (int32_t, 16) + TEST_LOOP (uint32_t, 16) + TEST_LOOP (int64_t, 16) + TEST_LOOP (uint64_t, 16) + + TEST_LOOP (int8_t, 77) + TEST_LOOP (uint8_t, 77) + TEST_LOOP (int16_t, 77) + TEST_LOOP (uint16_t, 77) + TEST_LOOP (int32_t, 77) + TEST_LOOP (uint32_t, 77) + TEST_LOOP (int64_t, 77) + TEST_LOOP (uint64_t, 77) + + TEST_LOOP (int8_t, 128) + TEST_LOOP (uint8_t, 128) + TEST_LOOP (int16_t, 128) + TEST_LOOP (uint16_t, 128) + TEST_LOOP (int32_t, 128) + TEST_LOOP (uint32_t, 128) + TEST_LOOP (int64_t, 128) + TEST_LOOP (uint64_t, 128) + + TEST_LOOP (int8_t, 15641) + TEST_LOOP (uint8_t, 15641) + TEST_LOOP (int16_t, 15641) + TEST_LOOP (uint16_t, 15641) + TEST_LOOP (int32_t, 15641) + TEST_LOOP (uint32_t, 15641) + TEST_LOOP (int64_t, 15641) + TEST_LOOP (uint64_t, 15641) + + TEST_LOOP (int8_t, 795) + TEST_LOOP (uint8_t, 795) + TEST_LOOP (int16_t, 795) + TEST_LOOP (uint16_t, 795) + TEST_LOOP (int32_t, 795) + TEST_LOOP (uint32_t, 795) + TEST_LOOP (int64_t, 795) + TEST_LOOP (uint64_t, 795) + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c new file mode 100644 index 00000000000..f9bdf92cc2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c @@ -0,0 +1,104 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ + +#include "ternop-5.c" + +#define TEST_LOOP(TYPE, NUM) \ + { \ + TYPE array1_##NUM[NUM] = {}; \ + TYPE array2_##NUM[NUM] = {}; \ + TYPE array3_##NUM[NUM] = {}; \ + TYPE array4_##NUM[NUM] = {}; \ + TYPE array5_##NUM[NUM] = {}; \ + TYPE array6_##NUM[NUM] = {}; \ + TYPE array7_##NUM[NUM] = {}; \ + TYPE array8_##NUM[NUM] = {}; \ + for (int i = 0; i < NUM; ++i) \ + { \ + array1_##NUM[i] = (i & 1) + 5; \ + array2_##NUM[i] = i - NUM / 3; \ + array3_##NUM[i] = NUM - NUM / 3 - i; \ + array6_##NUM[i] = NUM - NUM / 3 - i; \ + array4_##NUM[i] = NUM - NUM / 2 + i; \ + array7_##NUM[i] = NUM - NUM / 2 + i; \ + array5_##NUM[i] = NUM + i * 7; \ + array8_##NUM[i] = NUM + i * 7; \ + asm volatile("" ::: "memory"); \ + } \ + ternop_##TYPE (array3_##NUM, array4_##NUM, array5_##NUM, array1_##NUM, \ + array2_##NUM, NUM); \ + for (int i = 0; i < NUM; i++) \ + { \ + array6_##NUM[i] \ + = (TYPE) (-(array1_##NUM[i] * array2_##NUM[i]) + array6_##NUM[i]); \ + if (array3_##NUM[i] != array6_##NUM[i]) \ + __builtin_abort (); \ + array7_##NUM[i] \ + = (TYPE) (array1_##NUM[i] * array6_##NUM[i] + array7_##NUM[i]); \ + if (array4_##NUM[i] != array7_##NUM[i]) \ + __builtin_abort (); \ + array8_##NUM[i] \ + = (TYPE) (array2_##NUM[i] * array7_##NUM[i] + array8_##NUM[i]); \ + if (array5_##NUM[i] != array8_##NUM[i]) \ + __builtin_abort (); \ + } \ + } + +int __attribute__ ((optimize (0))) main () +{ + TEST_LOOP (int8_t, 7) + TEST_LOOP (uint8_t, 7) + TEST_LOOP (int16_t, 7) + TEST_LOOP (uint16_t, 7) + TEST_LOOP (int32_t, 7) + TEST_LOOP (uint32_t, 7) + TEST_LOOP (int64_t, 7) + TEST_LOOP (uint64_t, 7) + + TEST_LOOP (int8_t, 16) + TEST_LOOP (uint8_t, 16) + TEST_LOOP (int16_t, 16) + TEST_LOOP (uint16_t, 16) + TEST_LOOP (int32_t, 16) + TEST_LOOP (uint32_t, 16) + TEST_LOOP (int64_t, 16) + TEST_LOOP (uint64_t, 16) + + TEST_LOOP (int8_t, 77) + TEST_LOOP (uint8_t, 77) + TEST_LOOP (int16_t, 77) + TEST_LOOP (uint16_t, 77) + TEST_LOOP (int32_t, 77) + TEST_LOOP (uint32_t, 77) + TEST_LOOP (int64_t, 77) + TEST_LOOP (uint64_t, 77) + + TEST_LOOP (int8_t, 128) + TEST_LOOP (uint8_t, 128) + TEST_LOOP (int16_t, 128) + TEST_LOOP (uint16_t, 128) + TEST_LOOP (int32_t, 128) + TEST_LOOP (uint32_t, 128) + TEST_LOOP (int64_t, 128) + TEST_LOOP (uint64_t, 128) + + TEST_LOOP (int8_t, 15641) + TEST_LOOP (uint8_t, 15641) + TEST_LOOP (int16_t, 15641) + TEST_LOOP (uint16_t, 15641) + TEST_LOOP (int32_t, 15641) + TEST_LOOP (uint32_t, 15641) + TEST_LOOP (int64_t, 15641) + TEST_LOOP (uint64_t, 15641) + + TEST_LOOP (int8_t, 795) + TEST_LOOP (uint8_t, 795) + TEST_LOOP (int16_t, 795) + TEST_LOOP (uint16_t, 795) + TEST_LOOP (int32_t, 795) + TEST_LOOP (uint32_t, 795) + TEST_LOOP (int64_t, 795) + TEST_LOOP (uint64_t, 795) + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c new file mode 100644 index 00000000000..c000e331084 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c @@ -0,0 +1,104 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */ + +#include "ternop-6.c" + +#define TEST_LOOP(TYPE, NUM) \ + { \ + TYPE array1_##NUM[NUM] = {}; \ + TYPE array2_##NUM[NUM] = {}; \ + TYPE array3_##NUM[NUM] = {}; \ + TYPE array4_##NUM[NUM] = {}; \ + TYPE array5_##NUM[NUM] = {}; \ + TYPE array6_##NUM[NUM] = {}; \ + TYPE array7_##NUM[NUM] = {}; \ + TYPE array8_##NUM[NUM] = {}; \ + for (int i = 0; i < NUM; ++i) \ + { \ + array1_##NUM[i] = (i & 1) + 5; \ + array2_##NUM[i] = i - NUM / 3; \ + array3_##NUM[i] = NUM - NUM / 3 - i; \ + array6_##NUM[i] = NUM - NUM / 3 - i; \ + array4_##NUM[i] = NUM - NUM / 2 + i; \ + array7_##NUM[i] = NUM - NUM / 2 + i; \ + array5_##NUM[i] = NUM + i * 7; \ + array8_##NUM[i] = NUM + i * 7; \ + asm volatile("" ::: "memory"); \ + } \ + ternop_##TYPE (array3_##NUM, array4_##NUM, array5_##NUM, array1_##NUM, \ + array2_##NUM, NUM); \ + for (int i = 0; i < NUM; i++) \ + { \ + array6_##NUM[i] \ + = (TYPE) (-(array1_##NUM[i] * array2_##NUM[i]) + array7_##NUM[i]); \ + if (array3_##NUM[i] != array6_##NUM[i]) \ + __builtin_abort (); \ + array7_##NUM[i] \ + = (TYPE) (array1_##NUM[i] * array6_##NUM[i] + array7_##NUM[i]); \ + if (array4_##NUM[i] != array7_##NUM[i]) \ + __builtin_abort (); \ + array8_##NUM[i] \ + = (TYPE) (array2_##NUM[i] * array7_##NUM[i] + array8_##NUM[i]); \ + if (array5_##NUM[i] != array8_##NUM[i]) \ + __builtin_abort (); \ + } \ + } + +int __attribute__ ((optimize (0))) main () +{ + TEST_LOOP (int8_t, 7) + TEST_LOOP (uint8_t, 7) + TEST_LOOP (int16_t, 7) + TEST_LOOP (uint16_t, 7) + TEST_LOOP (int32_t, 7) + TEST_LOOP (uint32_t, 7) + TEST_LOOP (int64_t, 7) + TEST_LOOP (uint64_t, 7) + + TEST_LOOP (int8_t, 16) + TEST_LOOP (uint8_t, 16) + TEST_LOOP (int16_t, 16) + TEST_LOOP (uint16_t, 16) + TEST_LOOP (int32_t, 16) + TEST_LOOP (uint32_t, 16) + TEST_LOOP (int64_t, 16) + TEST_LOOP (uint64_t, 16) + + TEST_LOOP (int8_t, 77) + TEST_LOOP (uint8_t, 77) + TEST_LOOP (int16_t, 77) + TEST_LOOP (uint16_t, 77) + TEST_LOOP (int32_t, 77) + TEST_LOOP (uint32_t, 77) + TEST_LOOP (int64_t, 77) + TEST_LOOP (uint64_t, 77) + + TEST_LOOP (int8_t, 128) + TEST_LOOP (uint8_t, 128) + TEST_LOOP (int16_t, 128) + TEST_LOOP (uint16_t, 128) + TEST_LOOP (int32_t, 128) + TEST_LOOP (uint32_t, 128) + TEST_LOOP (int64_t, 128) + TEST_LOOP (uint64_t, 128) + + TEST_LOOP (int8_t, 15641) + TEST_LOOP (uint8_t, 15641) + TEST_LOOP (int16_t, 15641) + TEST_LOOP (uint16_t, 15641) + TEST_LOOP (int32_t, 15641) + TEST_LOOP (uint32_t, 15641) + TEST_LOOP (int64_t, 15641) + TEST_LOOP (uint64_t, 15641) + + TEST_LOOP (int8_t, 795) + TEST_LOOP (uint8_t, 795) + TEST_LOOP (int16_t, 795) + TEST_LOOP (uint16_t, 795) + TEST_LOOP (int32_t, 795) + TEST_LOOP (uint32_t, 795) + TEST_LOOP (int64_t, 795) + TEST_LOOP (uint64_t, 795) + + return 0; +}