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[8.43.85.97]) by mx.google.com with ESMTPS id si10-20020a170906ceca00b0096f805b6ab6si1374651ejb.860.2023.05.25.16.19.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:19:16 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DD5D0388201B for ; Thu, 25 May 2023 23:18:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18]) by sourceware.org (Postfix) with ESMTPS id 94638385770F for ; Thu, 25 May 2023 23:17:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 94638385770F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp91t1685056663tdf2jjas Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 26 May 2023 07:17:41 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: bhet8yMU7vmTf/1Nib7MPWJb7eh+0UXrq8vFM6G+2NyPNlP5Ih3Br0v7sJlyp jSZInSz+c3o4p+6Smj8b2uX8yib4+S1CEUVjz9uwRE5rgjxoq1Fvxtt/xElhtoO2nNN04T7 eWAYNE6juasI74wwPuFuIAUgMT2KNSMasqWHrjFdyORZ45WTYkSkvCTrPU6PoKcfH0Sp545 dH83BOHVbVtCydIKKPMP6CZ6xLwRZoGM13Mr8FmF3qRIJrZW9MEgk5BpxKooJAl9A1NvFXT NxHqoyrF7cY1p8xG13HGJcEmzSMRotzuZLB26ljbYHQYh5ZsUOA1Bttq3WR88TgAzY+16hE SO2eHt6B0fH4v6Ipi6D1P5ARXWL3rxMu/cDkDmpohkG1EE+uj+OqidMhuvORA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 13305096490252379148 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: jlaw@ventanamicro.com, jeffreyalaw@gmail.com, kito.cheng@sifive.com, kito.cheng@gmail.com, palmer@rivosinc.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix zero-scratch-regs-3.c fail Date: Fri, 26 May 2023 07:17:40 +0800 Message-Id: <20230525231740.2405092-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766910072986625826?= X-GMAIL-MSGID: =?utf-8?q?1766910072986625826?= From: Juzhe-Zhong Fix ICE of zero-scratch-regs-3.c: bug.c:7:1: internal compiler error: Segmentation fault 7 | } | ^ 0x1647b23 crash_signal ../../../riscv-gcc/gcc/toplev.cc:314 0x147053f maybe_legitimize_operand ../../../riscv-gcc/gcc/optabs.cc:7947 0x1470dc2 maybe_legitimize_operands(insn_code, unsigned int, unsigned int, expand_operand*) ../../../riscv-gcc/gcc/optabs.cc:8084 0x1470e66 maybe_gen_insn(insn_code, unsigned int, expand_operand*) ../../../riscv-gcc/gcc/optabs.cc:8103 0x147146a maybe_expand_insn(insn_code, unsigned int, expand_operand*) ../../../riscv-gcc/gcc/optabs.cc:8158 0x14714fe expand_insn(insn_code, unsigned int, expand_operand*) ../../../riscv-gcc/gcc/optabs.cc:8189 0x1c20634 riscv_vector::insn_expander<11>::expand(insn_code, bool) ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:210 0x1c20075 riscv_vector::insn_expander<11>::emit_insn(insn_code, rtx_def**) ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:199 0x1c16bd1 riscv_vector::emit_vlmax_insn(unsigned int, int, rtx_def**, rtx_def*) ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:362 0x1ad5bb9 vector_zero_call_used_regs ../../../riscv-gcc/gcc/config/riscv/riscv.cc:7400 0x1ad5c25 riscv_zero_call_used_regs(HARD_REG_SET) ../../../riscv-gcc/gcc/config/riscv/riscv.cc:7420 0x115c910 gen_call_used_regs_seq ../../../riscv-gcc/gcc/function.cc:5924 0x115df81 execute ../../../riscv-gcc/gcc/function.cc:6718 ICE happens since we didn't pass explicit VL operand when we can't use gen_reg_rtx to generate VL operand. This will make operands num mismatch. gcc/ChangeLog: * config/riscv/riscv.cc (vector_zero_call_used_regs): Add explicit VL operand. --- gcc/config/riscv/riscv.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 09fc9e5d95e..9e41200371d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7398,7 +7398,7 @@ vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) rtx ops[] = {target, CONST0_RTX (mode), vl}; riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), - riscv_vector::RVV_UNOP, ops); + riscv_vector::RVV_UNOP, ops, vl); SET_HARD_REG_BIT (zeroed_hardregs, regno); }