From patchwork Thu May 25 12:46:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 99008 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp339276vqr; Thu, 25 May 2023 05:46:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4pNCHYS454LH3hPErS54p6+//W4jufiMLIXUcadvSl0ZdkibIWeJZvP4FkRI73Rxw+1qC2 X-Received: by 2002:aa7:c252:0:b0:510:6217:9994 with SMTP id y18-20020aa7c252000000b0051062179994mr4327326edo.39.1685018817959; Thu, 25 May 2023 05:46:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685018817; cv=none; d=google.com; s=arc-20160816; b=Oxhj6KhMhZVIsqh6/72W/skTZ0ydc/K3Wb5jaal9UD1yY6NwVDc4EwB6QSlBbA0FkX AeQxrSW0ZB7oNK5DD5ZtCLVrGRCI8BX0pcH9jWeKD2bGrC4Zsmz79DMsXvLcNwpEyF0G JKDX3DzLhpi0aL8EycFFVFW1cdzG23YOCPvj9nCV/VEUJrZXUon0aIxULEZz15ZasXBq +8DMtYCacRWj9ym/wvtY3bw8vv0vDN3BJG0LUJw72Pi9Tl+RSqenciUKcCLa53r46FlH TmOuPSHDuMypsLr0hsedqJFugR/eeHDwPMm9z+xa9c79PWv4fzqihJxpqIGVb75QEnpv 446g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=1SLeKoKRstzQ+0gpsRgcYGHdhYCRhsyr2CjFhOF/yjc=; b=wRCU1kvEyUbjAs01OedF0bIYz20HLsd1SFNH33DY9KoCCTDrGDZP38OTw+AJSnKwRe tjVaBe8TksTbf5U+DaYtuFVlcgQsJD/S8Yyc6It0xoKvmAg/oie/ebralEe39kXB6ovm Yz9BX/35siZ6AcbykGM4W/UsycJvh1V1sn8HcEG4PJu7H+8PLRt5r26YomFtYd1jxIsj kNi3HeBcWkoWfArNw3oGScF3m2j20zGQkEjhIDWzbxrK9lzs3Yk/myjfHh+TMb8FNQSJ Edj7oFYskruPF4XtPeWn4AoN3RPoHrvF2NRTldhfn5Sgu5l7AWlAWZ27XndjjEyuz+7k N9aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ntgbNCPi; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id i23-20020a50fc17000000b0051425b17840si792845edr.664.2023.05.25.05.46.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 05:46:57 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ntgbNCPi; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DDD843857703 for ; Thu, 25 May 2023 12:46:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DDD843857703 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685018816; bh=1SLeKoKRstzQ+0gpsRgcYGHdhYCRhsyr2CjFhOF/yjc=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=ntgbNCPi+3cfC2fsDQnNgeEwZdjMy4h++urjZtMwV0+w5DZ1uE2ka0rCSy9/GogIJ qIoA4UFO4aSpBUNdLxyPmf+slMWEasyuS4MUOuvxrkpENmtsK9DsQEUw0JVf8fHI8N kwIZmhTOD7wonm1T9MpvxcI4EVW2aP4+6pGr1TCU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id C606B385842C for ; Thu, 25 May 2023 12:46:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C606B385842C X-IronPort-AV: E=McAfee;i="6600,9927,10721"; a="440229693" X-IronPort-AV: E=Sophos;i="6.00,191,1681196400"; d="scan'208";a="440229693" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2023 05:46:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10721"; a="737727792" X-IronPort-AV: E=Sophos;i="6.00,191,1681196400"; d="scan'208";a="737727792" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 25 May 2023 05:46:08 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 4303F1005043; Thu, 25 May 2023 20:46:08 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option Date: Thu, 25 May 2023 20:46:07 +0800 Message-Id: <20230525124607.787654-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766870291681782160?= X-GMAIL-MSGID: =?utf-8?q?1766870291681782160?= From: Pan Li This patch would like to add new sub extension (aka ZVFHMIN) to the -march= option. To make it simple, only the sub extension itself is involved in this patch, and the underlying FP16 related RVV intrinsic API depends on the TARGET_ZVFHMIN. You can locate more information about ZVFHMIN from below spec doc. https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point Signed-off-by: Pan Li gcc/ChangeLog: * common/config/riscv/riscv-common.cc: (riscv_implied_info): Add zvfhmin item. (riscv_ext_version_table): Ditto. (riscv_ext_flag_table): Ditto. * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro. (TARGET_ZFHMIN): Align indent. (TARGET_ZFH): Ditto. (TARGET_ZVFHMIN): New macro. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-20.c: New test. * gcc.target/riscv/predef-26.c: New test. Signed-off-by: Pan Li --- gcc/common/config/riscv/riscv-common.cc | 3 ++ gcc/config/riscv/riscv-opts.h | 6 ++- gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++ gcc/testsuite/gcc.target/riscv/predef-26.c | 51 ++++++++++++++++++++++ 4 files changed, 63 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index c2ec74b9d92..72f2f8f2753 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -104,6 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zfh", "zfhmin"}, {"zfhmin", "f"}, + {"zvfhmin", "f"}, {"zhinx", "zhinxmin"}, {"zhinxmin", "zfinx"}, @@ -216,6 +217,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zfh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0}, {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1259,6 +1261,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN}, {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH}, + {"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN}, {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 2a16402265a..f34ca993689 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -200,9 +200,11 @@ enum riscv_entity #define MASK_ZFHMIN (1 << 0) #define MASK_ZFH (1 << 1) +#define MASK_ZVFHMIN (1 << 2) -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0) -#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0) +#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0) +#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0) +#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0) #define MASK_ZMMUL (1 << 0) #define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0) diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c b/gcc/testsuite/gcc.target/riscv/arch-20.c new file mode 100644 index 00000000000..8f8da1ecd65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-20.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gcv_zvfhmin -mabi=ilp32 -mcmodel=medlow" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c b/gcc/testsuite/gcc.target/riscv/predef-26.c new file mode 100644 index 00000000000..285f64bd6c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/predef-26.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ + +int main () { + +#ifndef __riscv_arch_test +#error "__riscv_arch_test" +#endif + +#if __riscv_xlen != 64 +#error "__riscv_xlen" +#endif + +#if !defined(__riscv_i) +#error "__riscv_i" +#endif + +#if !defined(__riscv_f) +#error "__riscv_f" +#endif + +#if !defined(__riscv_zvfhmin) +#error "__riscv_zvfhmin" +#endif + +#if defined(__riscv_v) +#error "__riscv_v" +#endif + +#if defined(__riscv_d) +#error "__riscv_d" +#endif + +#if defined(__riscv_c) +#error "__riscv_c" +#endif + +#if defined(__riscv_a) +#error "__riscv_a" +#endif + +#if defined(__riscv_zfh) +#error "__riscv_zfh" +#endif + +#if defined(__riscv_zfhmin) +#error "__riscv_zfhmin" +#endif + + return 0; +}