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[8.43.85.97]) by mx.google.com with ESMTPS id g4-20020a17090670c400b0096f830337e9si674518ejk.193.2023.05.25.00.54.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 00:54:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EC2D83857344 for ; Thu, 25 May 2023 07:54:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id F3BE43858D28 for ; Thu, 25 May 2023 07:54:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F3BE43858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp83t1685001251t9c49klv Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 25 May 2023 15:54:09 +0800 (CST) X-QQ-SSF: 01400000000000F0R000000A0000000 X-QQ-FEAT: j86OQQvu8eSa7v4BvqChbnOtUD8RoYdoGCkcY+dbnTsWaBN042ZPVxw1CDvZW ViY4ThATiFcoO0BFgvi8IKudjlWPLFVRkc+S4LM8tlAPuEjfyDnXEDTEqt/uw9TvQKjMswW fk8VK/bulj0PfyTmMEienDS93H0DGv3gnSKuuJQ9GxH3nXMpTX9iid4u5KIAxic9wapp0+M BBMzXIzeUvIF9TfnLBQfCJXX+P4bjRNVbRR6FpeHISZw9SwT0PYYgr0hqHs+VOz6kbGDJDf U0stk8gkd4+azuXcqyaU318YEqn8vJHZnub6Ym6TVTvMbz2Ej9SA0CFKKPSGH8lb7i5egCz lr8IHVVatxp7bux9PzErq2UHTBcRnKHhC5E+Jn/phF0CIF1C0N6JgGNqERjZXcKY9b04us3 BSgEuTcH8VQ= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 17848153997941921890 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, pan2.li@intel.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add RVV FRM enum for floating-point rounding mode intriniscs Date: Thu, 25 May 2023 15:54:06 +0800 Message-Id: <20230525075406.270194-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766851918517156964?= X-GMAIL-MSGID: =?utf-8?q?1766851918517156964?= From: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (register_frm): New function. (DEF_RVV_FRM_ENUM): New macro. (handle_pragma_vector): Add FRM enum * config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro. (RNE): Ditto. (RTZ): Ditto. (RDN): Ditto. (RUP): Ditto. (RMM): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/frm-1.c: New test. --- gcc/config/riscv/riscv-vector-builtins.cc | 14 ++++++++ gcc/config/riscv/riscv-vector-builtins.def | 12 +++++++ .../gcc.target/riscv/rvv/base/frm-1.c | 35 +++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index f69f6c49c7e..9fea70709fd 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -4031,6 +4031,19 @@ register_vxrm () lang_hooks.types.simulate_enum_decl (input_location, "RVV_VXRM", &values); } +/* Register the frm enum. */ +static void +register_frm () +{ + auto_vec values; +#define DEF_RVV_FRM_ENUM(NAME, VALUE) \ + values.quick_push (string_int_pair ("FRM_" #NAME, VALUE)); +#include "riscv-vector-builtins.def" +#undef DEF_RVV_FRM_ENUM + + lang_hooks.types.simulate_enum_decl (input_location, "RVV_FRM", &values); +} + /* Implement #pragma riscv intrinsic vector. */ void handle_pragma_vector () @@ -4048,6 +4061,7 @@ handle_pragma_vector () /* Define the enums. */ register_vxrm (); + register_frm (); /* Define the functions. */ function_table = new hash_table (1023); diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 533853e09b1..61346e53d7b 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -94,6 +94,11 @@ along with GCC; see the file COPYING3. If not see #define DEF_RVV_VXRM_ENUM(NAME, VALUE) #endif +/* Define RVV_FRM rounding mode enum for floating-point intrinsics. */ +#ifndef DEF_RVV_FRM_ENUM +#define DEF_RVV_FRM_ENUM(NAME, VALUE) +#endif + /* SEW/LMUL = 64: Only enable when TARGET_MIN_VLEN > 32. Machine mode = VNx1BImode when TARGET_MIN_VLEN < 128. @@ -674,6 +679,12 @@ DEF_RVV_VXRM_ENUM (RNE, VXRM_RNE) DEF_RVV_VXRM_ENUM (RDN, VXRM_RDN) DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD) +DEF_RVV_FRM_ENUM (RNE, FRM_RNE) +DEF_RVV_FRM_ENUM (RTZ, FRM_RTZ) +DEF_RVV_FRM_ENUM (RDN, FRM_RDN) +DEF_RVV_FRM_ENUM (RUP, FRM_RUP) +DEF_RVV_FRM_ENUM (RMM, FRM_RMM) + #include "riscv-vector-type-indexer.gen.def" #undef DEF_RVV_PRED_TYPE @@ -683,3 +694,4 @@ DEF_RVV_VXRM_ENUM (ROD, VXRM_ROD) #undef DEF_RVV_BASE_TYPE #undef DEF_RVV_TYPE_INDEX #undef DEF_RVV_VXRM_ENUM +#undef DEF_RVV_FRM_ENUM diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c new file mode 100644 index 00000000000..f5635fb959e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/frm-1.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +size_t f0 () +{ + return FRM_RNE; +} + +size_t f1 () +{ + return FRM_RTZ; +} + +size_t f2 () +{ + return FRM_RDN; +} + +size_t f3 () +{ + return FRM_RUP; +} + +size_t f4 () +{ + return FRM_RMM; +} + +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */ +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*1} 1} } */ +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*2} 1} } */ +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*3} 1} } */ +/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*4} 1} } */