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[8.43.85.97]) by mx.google.com with ESMTPS id g19-20020a056402181300b00510e5603d4dsi1384010edy.140.2023.05.20.08.05.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 08:05:14 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="Hg89G/Kw"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3025A3854148 for ; Sat, 20 May 2023 15:05:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3025A3854148 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1684595101; bh=gaPDO2pA1PH+9xKIQzxBAQYvkg8/J489mmfw5EG0yj0=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=Hg89G/KwWT61b+Wk82cJLUIs5mceK94QuZs5p2xRijL+gWHQHjKN4Dx3hy6EhKGpu axVYF3oUW9Pnivq3tzHUSDl5E0I1tepHdQZ7B7IQP4xtbGFmFyZkqhWDCdXi8/6QPl RhOBmZtXublPOCku0RAkzgfAtlRIIZjNpgT/sO8A= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 9744F3858C52 for ; Sat, 20 May 2023 15:04:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9744F3858C52 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34KCirsr015805 for ; Sat, 20 May 2023 08:04:16 -0700 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3qpujn8keg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 20 May 2023 08:04:16 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sat, 20 May 2023 08:04:14 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sat, 20 May 2023 08:04:14 -0700 Received: from vpnclient.wrightpinski.org.com (unknown [10.69.242.187]) by maili.marvell.com (Postfix) with ESMTP id 4FC9A3F7088; Sat, 20 May 2023 08:04:14 -0700 (PDT) To: CC: Andrew Pinski Subject: [PATCHv2 1/2] Improve do_store_flag for single bit comparison against 0 Date: Sat, 20 May 2023 08:04:05 -0700 Message-ID: <20230520150406.1932767-1-apinski@marvell.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: QE-2CNY_4tBxnNDroKupBrlJJGenEs11 X-Proofpoint-GUID: QE-2CNY_4tBxnNDroKupBrlJJGenEs11 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-20_08,2023-05-17_02,2023-02-09_01 X-Spam-Status: No, score=-14.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrew Pinski via Gcc-patches From: Andrew Pinski Reply-To: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766426007083337029?= X-GMAIL-MSGID: =?utf-8?q?1766426007083337029?= While working something else, I noticed we could improve the following function code generation: ``` unsigned f(unsigned t) { if (t & ~(1<<30)) __builtin_unreachable(); return t != 0; } ``` Right know we just emit a comparison against 0 instead of just a shift right by 30. There is code in do_store_flag which already optimizes `(t & 1<<30) != 0` to `(t >> 30) & 1` (using bit extraction if available). This patch extends it to handle the case where we know t has a nonzero of just one bit set. Changes from v1: * v2: Updated for the bit extraction improvements. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: * expr.cc (do_store_flag): Extend the one bit checking case to handle the case where we don't have an and but rather still one bit is known to be non-zero. --- gcc/expr.cc | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/gcc/expr.cc b/gcc/expr.cc index 6849c9627d0..b85e963b57e 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -13155,16 +13155,31 @@ do_store_flag (sepops ops, rtx target, machine_mode mode) && integer_zerop (arg1) && (TYPE_PRECISION (ops->type) != 1 || TYPE_UNSIGNED (ops->type))) { - gimple *srcstmt = get_def_for_expr (arg0, BIT_AND_EXPR); - if (srcstmt - && integer_pow2p (gimple_assign_rhs2 (srcstmt))) + wide_int nz = tree_nonzero_bits (arg0); + + if (wi::popcount (nz) == 1) { + tree op0; + int bitnum; + gimple *srcstmt = get_def_for_expr (arg0, BIT_AND_EXPR); + /* If the defining statement was (x & POW2), then remove the and + as we are going to add it back. */ + if (srcstmt + && integer_pow2p (gimple_assign_rhs2 (srcstmt))) + { + op0 = gimple_assign_rhs1 (srcstmt); + bitnum = tree_log2 (gimple_assign_rhs2 (srcstmt)); + } + else + { + op0 = arg0; + bitnum = wi::exact_log2 (nz); + } enum tree_code tcode = code == NE ? NE_EXPR : EQ_EXPR; - int bitnum = tree_log2 (gimple_assign_rhs2 (srcstmt)); type = lang_hooks.types.type_for_mode (mode, unsignedp); return expand_single_bit_test (loc, tcode, - gimple_assign_rhs1 (srcstmt), + op0, bitnum, type, target, mode); } }