diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc
index 2f0375568a8..33738e41d7c 100644
--- a/gcc/config/riscv/genrvv-type-indexer.cc
+++ b/gcc/config/riscv/genrvv-type-indexer.cc
@@ -23,7 +23,7 @@ along with GCC; see the file COPYING3.  If not see
 #include <assert.h>
 #include <math.h>
 
-#define BOOL_SIZE_LIST {1}
+#define BOOL_SIZE_LIST {1, 2, 4, 8, 16, 32, 64}
 
 std::string
 to_lmul (int lmul_log2)
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 72032c6a52c..7c89a20cb24 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -509,6 +509,12 @@ DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_eew16_interpret_ops)
 DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_eew32_interpret_ops)
 DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_eew64_interpret_ops)
 DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool1_interpret_ops)
+DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool2_interpret_ops)
+DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool4_interpret_ops)
+DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool8_interpret_ops)
+DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool16_interpret_ops)
+DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool32_interpret_ops)
+DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool64_interpret_ops)
 DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x2_ops)
 DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x4_ops)
 DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x8_ops)
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
index 977ce6b1831..5d1e5164b60 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -187,6 +187,42 @@ along with GCC; see the file COPYING3. If not see
 #define DEF_RVV_BOOL1_INTERPRET_OPS(TYPE, REQUIRE)
 #endif
 
+/* Use "DEF_RVV_BOOL2_INTERPRET_OPS" macro include all types for BOOL2
+   vinterpret which will be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_BOOL2_INTERPRET_OPS
+#define DEF_RVV_BOOL2_INTERPRET_OPS(TYPE, REQUIRE)
+#endif
+
+/* Use "DEF_RVV_BOOL4_INTERPRET_OPS" macro include all types for BOOL4
+   vinterpret which will be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_BOOL4_INTERPRET_OPS
+#define DEF_RVV_BOOL4_INTERPRET_OPS(TYPE, REQUIRE)
+#endif
+
+/* Use "DEF_RVV_BOOL8_INTERPRET_OPS" macro include all types for BOOL8
+   vinterpret which will be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_BOOL8_INTERPRET_OPS
+#define DEF_RVV_BOOL8_INTERPRET_OPS(TYPE, REQUIRE)
+#endif
+
+/* Use "DEF_RVV_BOOL16_INTERPRET_OPS" macro include all types for BOOL16
+   vinterpret which will be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_BOOL16_INTERPRET_OPS
+#define DEF_RVV_BOOL16_INTERPRET_OPS(TYPE, REQUIRE)
+#endif
+
+/* Use "DEF_RVV_BOOL32_INTERPRET_OPS" macro include all types for BOOL32
+   vinterpret which will be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_BOOL32_INTERPRET_OPS
+#define DEF_RVV_BOOL32_INTERPRET_OPS(TYPE, REQUIRE)
+#endif
+
+/* Use "DEF_RVV_BOOL64_INTERPRET_OPS" macro include all types for BOOL64
+   vinterpret which will be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_BOOL64_INTERPRET_OPS
+#define DEF_RVV_BOOL64_INTERPRET_OPS(TYPE, REQUIRE)
+#endif
+
 /* Use "DEF_RVV_X2_VLMUL_EXT_OPS" macro include all types for X2 VLMUL EXT
    which will be iterated and registered as intrinsic functions.  */
 #ifndef DEF_RVV_X2_VLMUL_EXT_OPS
@@ -675,12 +711,65 @@ DEF_RVV_BOOL1_INTERPRET_OPS (vint8m1_t, 0)
 DEF_RVV_BOOL1_INTERPRET_OPS (vint16m1_t, 0)
 DEF_RVV_BOOL1_INTERPRET_OPS (vint32m1_t, 0)
 DEF_RVV_BOOL1_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
-
 DEF_RVV_BOOL1_INTERPRET_OPS (vuint8m1_t, 0)
 DEF_RVV_BOOL1_INTERPRET_OPS (vuint16m1_t, 0)
 DEF_RVV_BOOL1_INTERPRET_OPS (vuint32m1_t, 0)
 DEF_RVV_BOOL1_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
 
+DEF_RVV_BOOL2_INTERPRET_OPS (vint8m1_t, 0)
+DEF_RVV_BOOL2_INTERPRET_OPS (vint16m1_t, 0)
+DEF_RVV_BOOL2_INTERPRET_OPS (vint32m1_t, 0)
+DEF_RVV_BOOL2_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_BOOL2_INTERPRET_OPS (vuint8m1_t, 0)
+DEF_RVV_BOOL2_INTERPRET_OPS (vuint16m1_t, 0)
+DEF_RVV_BOOL2_INTERPRET_OPS (vuint32m1_t, 0)
+DEF_RVV_BOOL2_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+
+DEF_RVV_BOOL4_INTERPRET_OPS (vint8m1_t, 0)
+DEF_RVV_BOOL4_INTERPRET_OPS (vint16m1_t, 0)
+DEF_RVV_BOOL4_INTERPRET_OPS (vint32m1_t, 0)
+DEF_RVV_BOOL4_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_BOOL4_INTERPRET_OPS (vuint8m1_t, 0)
+DEF_RVV_BOOL4_INTERPRET_OPS (vuint16m1_t, 0)
+DEF_RVV_BOOL4_INTERPRET_OPS (vuint32m1_t, 0)
+DEF_RVV_BOOL4_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+
+DEF_RVV_BOOL8_INTERPRET_OPS (vint8m1_t, 0)
+DEF_RVV_BOOL8_INTERPRET_OPS (vint16m1_t, 0)
+DEF_RVV_BOOL8_INTERPRET_OPS (vint32m1_t, 0)
+DEF_RVV_BOOL8_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_BOOL8_INTERPRET_OPS (vuint8m1_t, 0)
+DEF_RVV_BOOL8_INTERPRET_OPS (vuint16m1_t, 0)
+DEF_RVV_BOOL8_INTERPRET_OPS (vuint32m1_t, 0)
+DEF_RVV_BOOL8_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+
+DEF_RVV_BOOL16_INTERPRET_OPS (vint8m1_t, 0)
+DEF_RVV_BOOL16_INTERPRET_OPS (vint16m1_t, 0)
+DEF_RVV_BOOL16_INTERPRET_OPS (vint32m1_t, 0)
+DEF_RVV_BOOL16_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_BOOL16_INTERPRET_OPS (vuint8m1_t, 0)
+DEF_RVV_BOOL16_INTERPRET_OPS (vuint16m1_t, 0)
+DEF_RVV_BOOL16_INTERPRET_OPS (vuint32m1_t, 0)
+DEF_RVV_BOOL16_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+
+DEF_RVV_BOOL32_INTERPRET_OPS (vint8m1_t, 0)
+DEF_RVV_BOOL32_INTERPRET_OPS (vint16m1_t, 0)
+DEF_RVV_BOOL32_INTERPRET_OPS (vint32m1_t, 0)
+DEF_RVV_BOOL32_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_BOOL32_INTERPRET_OPS (vuint8m1_t, 0)
+DEF_RVV_BOOL32_INTERPRET_OPS (vuint16m1_t, 0)
+DEF_RVV_BOOL32_INTERPRET_OPS (vuint32m1_t, 0)
+DEF_RVV_BOOL32_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+
+DEF_RVV_BOOL64_INTERPRET_OPS (vint8m1_t, 0)
+DEF_RVV_BOOL64_INTERPRET_OPS (vint16m1_t, 0)
+DEF_RVV_BOOL64_INTERPRET_OPS (vint32m1_t, 0)
+DEF_RVV_BOOL64_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_BOOL64_INTERPRET_OPS (vuint8m1_t, 0)
+DEF_RVV_BOOL64_INTERPRET_OPS (vuint16m1_t, 0)
+DEF_RVV_BOOL64_INTERPRET_OPS (vuint32m1_t, 0)
+DEF_RVV_BOOL64_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
+
 DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf4_t, 0)
 DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf2_t, 0)
@@ -1069,6 +1158,12 @@ DEF_RVV_TUPLE_OPS (vfloat64m4x2_t, RVV_REQUIRE_ELEN_FP_64)
 #undef DEF_RVV_EEW32_INTERPRET_OPS
 #undef DEF_RVV_EEW64_INTERPRET_OPS
 #undef DEF_RVV_BOOL1_INTERPRET_OPS
+#undef DEF_RVV_BOOL2_INTERPRET_OPS
+#undef DEF_RVV_BOOL4_INTERPRET_OPS
+#undef DEF_RVV_BOOL8_INTERPRET_OPS
+#undef DEF_RVV_BOOL16_INTERPRET_OPS
+#undef DEF_RVV_BOOL32_INTERPRET_OPS
+#undef DEF_RVV_BOOL64_INTERPRET_OPS
 #undef DEF_RVV_X2_VLMUL_EXT_OPS
 #undef DEF_RVV_X4_VLMUL_EXT_OPS
 #undef DEF_RVV_X8_VLMUL_EXT_OPS
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 0fa6ef15fb3..859bd1c35ab 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -331,6 +331,48 @@ static const rvv_type_info bool1_interpret_ops[] = {
 #include "riscv-vector-builtins-types.def"
   {NUM_VECTOR_TYPES, 0}};
 
+/* A list of bool2 interpret will be registered for intrinsic functions.  */
+static const rvv_type_info bool2_interpret_ops[] = {
+#define DEF_RVV_BOOL2_INTERPRET_OPS(TYPE, REQUIRE)                             \
+  {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+  {NUM_VECTOR_TYPES, 0}};
+
+/* A list of bool4 interpret will be registered for intrinsic functions.  */
+static const rvv_type_info bool4_interpret_ops[] = {
+#define DEF_RVV_BOOL4_INTERPRET_OPS(TYPE, REQUIRE)                             \
+  {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+  {NUM_VECTOR_TYPES, 0}};
+
+/* A list of bool8 interpret will be registered for intrinsic functions.  */
+static const rvv_type_info bool8_interpret_ops[] = {
+#define DEF_RVV_BOOL8_INTERPRET_OPS(TYPE, REQUIRE)                             \
+  {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+  {NUM_VECTOR_TYPES, 0}};
+
+/* A list of bool16 interpret will be registered for intrinsic functions.  */
+static const rvv_type_info bool16_interpret_ops[] = {
+#define DEF_RVV_BOOL16_INTERPRET_OPS(TYPE, REQUIRE)                            \
+  {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+  {NUM_VECTOR_TYPES, 0}};
+
+/* A list of bool32 interpret will be registered for intrinsic functions.  */
+static const rvv_type_info bool32_interpret_ops[] = {
+#define DEF_RVV_BOOL32_INTERPRET_OPS(TYPE, REQUIRE)                            \
+  {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+  {NUM_VECTOR_TYPES, 0}};
+
+/* A list of bool64 interpret will be registered for intrinsic functions.  */
+static const rvv_type_info bool64_interpret_ops[] = {
+#define DEF_RVV_BOOL64_INTERPRET_OPS(TYPE, REQUIRE)                            \
+  {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+  {NUM_VECTOR_TYPES, 0}};
+
 /* A list of x2 vlmul ext will be registered for intrinsic functions.  */
 static const rvv_type_info vlmul_ext_x2_ops[] = {
 #define DEF_RVV_X2_VLMUL_EXT_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
@@ -1611,6 +1653,54 @@ static CONSTEXPR const rvv_op_info iu_v_bool1_interpret_ops
      rvv_arg_type_info (RVV_BASE_bool1_interpret), /* Return type */
      v_args					   /* Args */};
 
+/* A static operand information for vbool2_t func (vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info iu_v_bool2_interpret_ops
+  = {bool2_interpret_ops,			   /* Types */
+     OP_TYPE_v,					   /* Suffix */
+     rvv_arg_type_info (RVV_BASE_bool2_interpret), /* Return type */
+     v_args					   /* Args */};
+
+/* A static operand information for vbool4_t func (vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info iu_v_bool4_interpret_ops
+  = {bool4_interpret_ops,			   /* Types */
+     OP_TYPE_v,					   /* Suffix */
+     rvv_arg_type_info (RVV_BASE_bool4_interpret), /* Return type */
+     v_args					   /* Args */};
+
+/* A static operand information for vbool8_t func (vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info iu_v_bool8_interpret_ops
+  = {bool8_interpret_ops,			   /* Types */
+     OP_TYPE_v,					   /* Suffix */
+     rvv_arg_type_info (RVV_BASE_bool8_interpret), /* Return type */
+     v_args					   /* Args */};
+
+/* A static operand information for vbool16_t func (vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info iu_v_bool16_interpret_ops
+  = {bool16_interpret_ops,			    /* Types */
+     OP_TYPE_v,					    /* Suffix */
+     rvv_arg_type_info (RVV_BASE_bool16_interpret), /* Return type */
+     v_args					    /* Args */};
+
+/* A static operand information for vbool32_t func (vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info iu_v_bool32_interpret_ops
+  = {bool32_interpret_ops,			    /* Types */
+     OP_TYPE_v,					    /* Suffix */
+     rvv_arg_type_info (RVV_BASE_bool32_interpret), /* Return type */
+     v_args					    /* Args */};
+
+/* A static operand information for vbool64_t func (vector_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info iu_v_bool64_interpret_ops
+  = {bool64_interpret_ops,			    /* Types */
+     OP_TYPE_v,					    /* Suffix */
+     rvv_arg_type_info (RVV_BASE_bool64_interpret), /* Return type */
+     v_args					    /* Args */};
+
 /* A static operand information for vector_type func (vector_type)
  * function registration. */
 static CONSTEXPR const rvv_op_info all_v_vlmul_ext_x2_ops
@@ -2297,7 +2387,8 @@ static CONSTEXPR const function_type_info function_types[] = {
   DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED,             \
   DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1,      \
   EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET,           \
-  BOOL1_INTERPRET,                                                             \
+  BOOL1_INTERPRET, BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET,          \
+  BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET,                        \
   X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT,      \
   X64_VLMUL_EXT, TUPLE_SUBPART)                                                \
   {                                                                            \
@@ -2336,6 +2427,12 @@ static CONSTEXPR const function_type_info function_types[] = {
     VECTOR_TYPE_##EEW32_INTERPRET,                                             \
     VECTOR_TYPE_##EEW64_INTERPRET,                                             \
     VECTOR_TYPE_##BOOL1_INTERPRET,                                             \
+    VECTOR_TYPE_##BOOL2_INTERPRET,                                             \
+    VECTOR_TYPE_##BOOL4_INTERPRET,                                             \
+    VECTOR_TYPE_##BOOL8_INTERPRET,                                             \
+    VECTOR_TYPE_##BOOL16_INTERPRET,                                            \
+    VECTOR_TYPE_##BOOL32_INTERPRET,                                            \
+    VECTOR_TYPE_##BOOL64_INTERPRET,                                            \
     VECTOR_TYPE_##X2_VLMUL_EXT,                                                \
     VECTOR_TYPE_##X4_VLMUL_EXT,                                                \
     VECTOR_TYPE_##X8_VLMUL_EXT,                                                \
@@ -2638,6 +2735,12 @@ required_extensions_p (enum rvv_base_type type)
       case RVV_BASE_eew32_interpret:
       case RVV_BASE_eew64_interpret:
       case RVV_BASE_bool1_interpret:
+      case RVV_BASE_bool2_interpret:
+      case RVV_BASE_bool4_interpret:
+      case RVV_BASE_bool8_interpret:
+      case RVV_BASE_bool16_interpret:
+      case RVV_BASE_bool32_interpret:
+      case RVV_BASE_bool64_interpret:
       case RVV_BASE_vlmul_ext_x2:
       case RVV_BASE_vlmul_ext_x4:
       case RVV_BASE_vlmul_ext_x8:
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index b3bf067129e..cb409a8cab7 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -79,7 +79,8 @@ along with GCC; see the file COPYING3.  If not see
   DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED,             \
   DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1,      \
   EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET,           \
-  BOOL1_INTERPRET,                                                             \
+  BOOL1_INTERPRET, BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET,          \
+  BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET,                        \
   X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT,      \
   X64_VLMUL_EXT, TUPLE_SUBPART)
 #endif
@@ -636,6 +637,12 @@ DEF_RVV_BASE_TYPE (eew16_interpret, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (eew32_interpret, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (eew64_interpret, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (bool1_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool2_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool4_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool8_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool16_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool32_interpret, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (bool64_interpret, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (vlmul_ext_x2, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (vlmul_ext_x4, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (vlmul_ext_x8, get_vector_type (type_idx))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index ff5ef2af1bc..d4cf9d4a07e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -34,5 +34,53 @@ vbool1_t test_vreinterpret_v_u64m1_b1 (vuint64m1_t src) {
   return __riscv_vreinterpret_v_u64m1_b1 (src);
 }
 
-/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */
+vbool2_t test_vreinterpret_v_i8m1_b2 (vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b2 (src);
+}
+
+vbool4_t test_vreinterpret_v_i8m1_b4 (vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b4 (src);
+}
+
+vbool8_t test_vreinterpret_v_i8m1_b8 (vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b8 (src);
+}
+
+vbool16_t test_vreinterpret_v_i8m1_b16 (vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b16 (src);
+}
+
+vbool32_t test_vreinterpret_v_i8m1_b32 (vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b32 (src);
+}
+
+vbool64_t test_vreinterpret_v_i8m1_b64 (vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b64 (src);
+}
+
+vbool2_t test_vreinterpret_v_u8m1_b2 (vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b2 (src);
+}
+
+vbool4_t test_vreinterpret_v_u8m1_b4 (vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b4 (src);
+}
+
+vbool8_t test_vreinterpret_v_u8m1_b8 (vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b8 (src);
+}
+
+vbool16_t test_vreinterpret_v_u8m1_b16 (vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b16 (src);
+}
+
+vbool32_t test_vreinterpret_v_u8m1_b32 (vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b32 (src);
+}
+
+vbool64_t test_vreinterpret_v_u8m1_b64 (vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b64 (src);
+}
+
+/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */
