diff mbox series

RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions

Message ID 20230515122235.293830-2-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add FRM and rounding mode operand into floating-point ternary instructions |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai May 15, 2023, 12:22 p.m. UTC 
  From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

This patch is adding FRM and rounding mode into floating-point ternary instructions.
This patch should be merged after optabs.cc patch.

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Add default rounding mode.
        * config/riscv/vector.md: Add rounding mode operand and FRM_REGNUM.

---
 gcc/config/riscv/riscv-vector-builtins.cc |  7 +++
 gcc/config/riscv/vector.md                | 64 +++++++++++++++++------
 2 files changed, 55 insertions(+), 16 deletions(-)

Comments

Jeff Law May 15, 2023, 1:43 p.m. UTC | #1 
On 5/15/23 06:22, juzhe.zhong@rivai.ai wrote:
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
> 
> This patch is adding FRM and rounding mode into floating-point ternary instructions.
> This patch should be merged after optabs.cc patch.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Add default rounding mode.
>          * config/riscv/vector.md: Add rounding mode operand and FRM_REGNUM.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index f10f38f6425..b7458aaace6 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3460,6 +3460,13 @@  function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
   add_input_operand (Pmode, get_tail_policy_for_pred (pred));
   add_input_operand (Pmode, get_mask_policy_for_pred (pred));
   add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
+
+  /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
+     We add default rounding mode for the intrinsics that didn't model rounding
+     mode yet.  */
+  if (opno != insn_data[icode].n_generator_args)
+    add_input_operand (Pmode, const0_rtx);
+
   return generate_insn (icode);
 }
 
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0929d19d5ec..80f9ba9bd28 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -5902,8 +5902,10 @@ 
 	     (match_operand 7 "const_int_operand")
 	     (match_operand 8 "const_int_operand")
 	     (match_operand 9 "const_int_operand")
+	     (match_operand 10 "const_int_operand")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (mult:VF
 	      (match_operand:VF 2 "register_operand")
@@ -5927,8 +5929,10 @@ 
 	     (match_operand 6 "const_int_operand"        "  i,    i,  i,    i")
 	     (match_operand 7 "const_int_operand"        "  i,    i,  i,    i")
 	     (match_operand 8 "const_int_operand"        "  i,    i,  i,    i")
+	     (match_operand 9 "const_int_operand"        "  i,    i,  i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (mult:VF
 	      (match_operand:VF 2 "register_operand"     "  0,   vr,  0,   vr")
@@ -5958,8 +5962,10 @@ 
 	     (match_operand 6 "const_int_operand"        "  i,    i,  i,    i")
 	     (match_operand 7 "const_int_operand"        "  i,    i,  i,    i")
 	     (match_operand 8 "const_int_operand"        "  i,    i,  i,    i")
+	     (match_operand 9 "const_int_operand"        "  i,    i,  i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (mult:VF
 	      (match_operand:VF 2 "register_operand"     " vr,   vr, vr,   vr")
@@ -5989,8 +5995,10 @@ 
 	     (match_operand 7 "const_int_operand"        "    i,    i")
 	     (match_operand 8 "const_int_operand"        "    i,    i")
 	     (match_operand 9 "const_int_operand"        "    i,    i")
+	     (match_operand 10 "const_int_operand"       "    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (mult:VF
 	      (match_operand:VF 2 "register_operand"     "   vr,   vr")
@@ -6024,8 +6032,10 @@ 
 	     (match_operand 7 "const_int_operand")
 	     (match_operand 8 "const_int_operand")
 	     (match_operand 9 "const_int_operand")
+	     (match_operand 10 "const_int_operand")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (mult:VF
 	      (vec_duplicate:VF
@@ -6045,8 +6055,10 @@ 
 	     (match_operand 6 "const_int_operand"         "  i,    i,  i,    i")
 	     (match_operand 7 "const_int_operand"         "  i,    i,  i,    i")
 	     (match_operand 8 "const_int_operand"         "  i,    i,  i,    i")
+	     (match_operand 9 "const_int_operand"         "  i,    i,  i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (mult:VF
 	      (vec_duplicate:VF
@@ -6077,8 +6089,10 @@ 
 	     (match_operand 6 "const_int_operand"         "  i,    i,  i,    i")
 	     (match_operand 7 "const_int_operand"         "  i,    i,  i,    i")
 	     (match_operand 8 "const_int_operand"         "  i,    i,  i,    i")
+	     (match_operand 9 "const_int_operand"         "  i,    i,  i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (mult:VF
 	      (vec_duplicate:VF
@@ -6109,8 +6123,10 @@ 
 	     (match_operand 7 "const_int_operand"        "    i,    i")
 	     (match_operand 8 "const_int_operand"        "    i,    i")
 	     (match_operand 9 "const_int_operand"        "    i,    i")
+	     (match_operand 10 "const_int_operand"       "    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (mult:VF
 	      (vec_duplicate:VF
@@ -6144,8 +6160,10 @@ 
 	     (match_operand 7 "const_int_operand")
 	     (match_operand 8 "const_int_operand")
 	     (match_operand 9 "const_int_operand")
+	     (match_operand 10 "const_int_operand")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (neg:VF
 	      (mult:VF
@@ -6170,8 +6188,10 @@ 
 	     (match_operand 6 "const_int_operand"        "  i,    i,  i,    i")
 	     (match_operand 7 "const_int_operand"        "  i,    i,  i,    i")
 	     (match_operand 8 "const_int_operand"        "  i,    i,  i,    i")
+	     (match_operand 9 "const_int_operand"        "  i,    i,  i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (neg:VF
 	      (mult:VF
@@ -6202,8 +6222,10 @@ 
 	     (match_operand 6 "const_int_operand"        "  i,    i,  i,    i")
 	     (match_operand 7 "const_int_operand"        "  i,    i,  i,    i")
 	     (match_operand 8 "const_int_operand"        "  i,    i,  i,    i")
+	     (match_operand 9 "const_int_operand"        "  i,    i,  i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (neg:VF
 	      (mult:VF
@@ -6234,8 +6256,10 @@ 
 	     (match_operand 7 "const_int_operand"        "    i,    i")
 	     (match_operand 8 "const_int_operand"        "    i,    i")
 	     (match_operand 9 "const_int_operand"        "    i,    i")
+	     (match_operand 10 "const_int_operand"       "    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (neg:VF
 	      (mult:VF
@@ -6270,8 +6294,10 @@ 
 	     (match_operand 7 "const_int_operand")
 	     (match_operand 8 "const_int_operand")
 	     (match_operand 9 "const_int_operand")
+	     (match_operand 10 "const_int_operand")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (neg:VF
 	      (mult:VF
@@ -6292,8 +6318,10 @@ 
 	     (match_operand 6 "const_int_operand"         "  i,    i,  i,    i")
 	     (match_operand 7 "const_int_operand"         "  i,    i,  i,    i")
 	     (match_operand 8 "const_int_operand"         "  i,    i,  i,    i")
+	     (match_operand 9 "const_int_operand"         "  i,    i,  i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (neg:VF
 	      (mult:VF
@@ -6325,8 +6353,10 @@ 
 	     (match_operand 6 "const_int_operand"           "  i,    i,  i,    i")
 	     (match_operand 7 "const_int_operand"           "  i,    i,  i,    i")
 	     (match_operand 8 "const_int_operand"           "  i,    i,  i,    i")
+	     (match_operand 9 "const_int_operand"           "  i,    i,  i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (neg:VF
 	      (mult:VF
@@ -6358,8 +6388,10 @@ 
 	     (match_operand 7 "const_int_operand"           "    i,    i")
 	     (match_operand 8 "const_int_operand"           "    i,    i")
 	     (match_operand 9 "const_int_operand"           "    i,    i")
+	     (match_operand 10 "const_int_operand"          "    i,    i")
 	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	     (reg:SI VTYPE_REGNUM)
+	     (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VF
 	    (neg:VF
 	      (mult:VF