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[8.43.85.97]) by mx.google.com with ESMTPS id ho19-20020a1709070e9300b0096aa5389a3esi7302308ejc.453.2023.05.15.01.34.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 May 2023 01:34:34 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=UYKoJeIg; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 03CB63852751 for ; Mon, 15 May 2023 08:34:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 03CB63852751 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1684139648; bh=Pt8kkrFdxTFk064U9U8eB3980hTBs2nrs5bYUs5y8vg=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=UYKoJeIgwV8nx62gEXjXl4ikGvxxB86FJWEsk01Byv1iyxBz/kyamcssrtqpRVsrN ZuCvtIfKX8wloJ/eOTTvZF1UCjAhAV7CmPVHTfOkzEhAIQuEN+3JvW8c5f8bD158OL PfEBULjKWCNPZWQv5+xyHcV8AOqNcfcdIfGIR3ZA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id D8BC33858438 for ; Mon, 15 May 2023 08:33:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D8BC33858438 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="330762828" X-IronPort-AV: E=Sophos;i="5.99,276,1677571200"; d="scan'208";a="330762828" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2023 01:33:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="703903421" X-IronPort-AV: E=Sophos;i="5.99,276,1677571200"; d="scan'208";a="703903421" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga007.fm.intel.com with ESMTP; 15 May 2023 01:33:07 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id BE88110085BE; Mon, 15 May 2023 16:33:06 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v2] RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization Date: Mon, 15 May 2023 16:33:05 +0800 Message-Id: <20230515083305.2656202-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765743034049625573?= X-GMAIL-MSGID: =?utf-8?q?1765948443553327522?= From: Pan Li This patch is optimizing the AVL for VLS auto-vectorzation. Given below sample code: typedef int8_t vnx2qi __attribute__ ((vector_size (2))); __attribute__ ((noipa)) void f_vnx2qi (int8_t a, int8_t b, int8_t *out) { vnx2qi v = {a, b}; *(vnx2qi *) out = v; } Before this patch: f_vnx2qi: vsetvli a5,zero,e8,mf8,ta,ma vmv.v.x v1,a0 vslide1down.vx v1,v1,a1 vse8.v v1,0(a2) ret After this patch: f_vnx2qi: vsetivli zero,2,e8,mf8,ta,ma vmv.v.x v1,a0 vslide1down.vx v1,v1,a1 vse8.v v1,0(a2) ret Signed-off-by: Pan Li Co-authored-by: Juzhe-Zhong Co-authored-by: kito-cheng gcc/ChangeLog: * config/riscv/riscv-v.cc (const_vlmax_p): New function for deciding the mode is constant or not. (set_len_and_policy): Optimize VLS-VLMAX code gen to vsetivli. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vf_avl-1.c: New test. --- gcc/config/riscv/riscv-v.cc | 26 ++++++++++++++++--- .../gcc.target/riscv/rvv/base/vf_avl-1.c | 15 +++++++++++ 2 files changed, 38 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index b8dc333f54e..d65e7300303 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -50,6 +50,19 @@ using namespace riscv_vector; namespace riscv_vector { +/* Return true if vlmax is constant value and can be used in vsetivl. */ +static bool +const_vlmax_p (machine_mode mode) +{ + poly_uint64 nuints = GET_MODE_NUNITS (mode); + + return nuints.is_constant () + /* The vsetivli can only hold register 0~31. */ + ? (IN_RANGE (nuints.to_constant (), 0, 31)) + /* Only allowed in VLS-VLMAX mode. */ + : false; +} + template class insn_expander { public: @@ -101,12 +114,19 @@ public: void set_len_and_policy (rtx len, bool force_vlmax = false) { - bool vlmax_p = force_vlmax; + bool vlmax_p = force_vlmax || !len; gcc_assert (has_dest); - if (!len) + if (vlmax_p && const_vlmax_p (dest_mode)) + { + /* Optimize VLS-VLMAX code gen, we can use vsetivli instead of the + vsetvli to obtain the value of vlmax. */ + poly_uint64 nunits = GET_MODE_NUNITS (dest_mode); + len = gen_int_mode (nunits, Pmode); + vlmax_p = false; /* It has became NONVLMAX now. */ + } + else if (!len) { - vlmax_p = true; len = gen_reg_rtx (Pmode); emit_vlmax_vsetvl (dest_mode, len); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c new file mode 100644 index 00000000000..11adf6bc611 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vf_avl-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax" } */ + +#include + +typedef int8_t vnx2qi __attribute__ ((vector_size (2))); + +__attribute__ ((noipa)) void +f_vnx2qi (int8_t a, int8_t b, int8_t *out) +{ + vnx2qi v = {a, b}; + *(vnx2qi *) out = v; +} + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*2,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 } } */