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[8.43.85.97]) by mx.google.com with ESMTPS id d5-20020a1709064c4500b0094375873121si6452143ejw.776.2023.05.11.22.01.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 22:01:13 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=DCzoqgV7; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ADF1F385B50D for ; Fri, 12 May 2023 05:01:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org ADF1F385B50D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683867671; bh=rsy1vk/uvAAAfQ7w9zo7wBDiPErfkA0qfU2Q6KCRLsU=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=DCzoqgV7St8rde89RfqQErjcceLQ6ZQkZk74m2nxfieq9Jy75jmCIu5xFpxLr15nr VJAXxgTDCxpheNK2FS9L57+wZ0oYLkGVHqprunAkhzJIbXrk2/Nek9YC9TGKjfv6Ij xv56ws1tsPSR1r9tV4qsUzUqQunD7yio+4jtTYBQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 6A52E3858C5E for ; Fri, 12 May 2023 05:00:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6A52E3858C5E X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="352948291" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="352948291" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 22:00:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="1029919251" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="1029919251" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga005.fm.intel.com with ESMTP; 11 May 2023 22:00:21 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 960401007BC8; Fri, 12 May 2023 13:00:20 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com, jeffreyalaw@gmail.com, rguenther@suse.de, richard.sandiford@arm.com Subject: [PATCH] Machine_Mode: Extend machine_mode from 8 to 16 bits Date: Fri, 12 May 2023 13:00:16 +0800 Message-Id: <20230512050016.476110-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765663230047271727?= X-GMAIL-MSGID: =?utf-8?q?1765663230047271727?= From: Pan Li We are running out of the machine_mode(8 bits) in RISC-V backend. Thus we would like to extend the machine mode bit size from 8 to 16 bits. However, it is sensitive to extend the memory size in common structure like tree or rtx. This patch would like to extend the machine mode bits to 16 bits by shrinking, like: * Swap the bit size of code and machine code in rtx_def. * Reconcile the machine_mode location and spare in tree. The memory impact of this patch for correlated structure looks like below: +-------------------+----------+---------+------+ | struct/bytes | upstream | patched | diff | +-------------------+----------+---------+------+ | rtx_obj_reference | 8 | 12 | +4 | | ext_modified | 2 | 3 | +1 | | ira_allocno | 192 | 200 | +8 | | qty_table_elem | 40 | 40 | 0 | | reg_stat_type | 64 | 64 | 0 | | rtx_def | 40 | 40 | 0 | | table_elt | 80 | 80 | 0 | | tree_decl_common | 112 | 112 | 0 | | tree_type_common | 128 | 128 | 0 | +-------------------+----------+---------+------+ The tree and rtx related struct has no memory changes after this patch, and the machine_mode changes to 16 bits already. Signed-off-by: Pan Li Co-authored-by: Ju-Zhe Zhong Co-authored-by: Kito Cheng gcc/ChangeLog: * combine.cc (struct reg_stat_type): Extended machine mode to 16 bits. * cse.cc (struct qty_table_elem): Ditto. (struct table_elt): Ditto. (struct set): Ditto. * genopinit.cc (main): Reconciled the machine mode limit. * ira-int.h (struct ira_allocno): Extended machine mode to 16 bits. * ree.cc (struct ATTRIBUTE_PACKED): Ditto. * rtl-ssa/accesses.h: Ditto. * rtl.h (RTX_CODE_BITSIZE): New macro. (RTX_MACHINE_MODE_BITSIZE): Ditto. (struct GTY): Swap bit size between code and machine mode. (subreg_shape::unique_id): Reconciled the machine mode limit. * rtlanal.h: Extended machine mode to 16 bits. * tree-core.h (struct tree_type_common): Ditto. (struct tree_decl_common): Reconciled the locate and extended bit size of machine mode. --- gcc/combine.cc | 4 ++-- gcc/cse.cc | 8 ++++---- gcc/genopinit.cc | 3 ++- gcc/ira-int.h | 12 ++++++++---- gcc/ree.cc | 2 +- gcc/rtl-ssa/accesses.h | 6 ++++-- gcc/rtl.h | 9 ++++++--- gcc/rtlanal.h | 5 +++-- gcc/tree-core.h | 11 ++++++++--- 9 files changed, 38 insertions(+), 22 deletions(-) diff --git a/gcc/combine.cc b/gcc/combine.cc index 5aa0ec5c45a..bdf6f635c80 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -200,7 +200,7 @@ struct reg_stat_type { unsigned HOST_WIDE_INT last_set_nonzero_bits; char last_set_sign_bit_copies; - ENUM_BITFIELD(machine_mode) last_set_mode : 8; + ENUM_BITFIELD(machine_mode) last_set_mode : RTX_MACHINE_MODE_BITSIZE; /* Set nonzero if references to register n in expressions should not be used. last_set_invalid is set nonzero when this register is being @@ -235,7 +235,7 @@ struct reg_stat_type { truncation if we know that value already contains a truncated value. */ - ENUM_BITFIELD(machine_mode) truncated_to_mode : 8; + ENUM_BITFIELD(machine_mode) truncated_to_mode : RTX_MACHINE_MODE_BITSIZE; }; diff --git a/gcc/cse.cc b/gcc/cse.cc index b10c9b0c94d..fe594c1bc3d 100644 --- a/gcc/cse.cc +++ b/gcc/cse.cc @@ -250,8 +250,8 @@ struct qty_table_elem unsigned int first_reg, last_reg; /* The sizes of these fields should match the sizes of the code and mode fields of struct rtx_def (see rtl.h). */ - ENUM_BITFIELD(rtx_code) comparison_code : 16; - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(rtx_code) comparison_code : RTX_CODE_BITSIZE; + ENUM_BITFIELD(machine_mode) mode : RTX_MACHINE_MODE_BITSIZE; }; /* The table of all qtys, indexed by qty number. */ @@ -406,7 +406,7 @@ struct table_elt int regcost; /* The size of this field should match the size of the mode field of struct rtx_def (see rtl.h). */ - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : RTX_MACHINE_MODE_BITSIZE; char in_memory; char is_const; char flag; @@ -4155,7 +4155,7 @@ struct set /* Original machine mode, in case it becomes a CONST_INT. The size of this field should match the size of the mode field of struct rtx_def (see rtl.h). */ - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : RTX_MACHINE_MODE_BITSIZE; /* Hash value of constant equivalent for SET_SRC. */ unsigned src_const_hash; /* A constant equivalent for SET_SRC, if any. */ diff --git a/gcc/genopinit.cc b/gcc/genopinit.cc index 83cb7504fa1..2add8b925da 100644 --- a/gcc/genopinit.cc +++ b/gcc/genopinit.cc @@ -182,7 +182,8 @@ main (int argc, const char **argv) progname = "genopinit"; - if (NUM_OPTABS > 0xffff || MAX_MACHINE_MODE >= 0xff) + if (NUM_OPTABS > 0xffff + || MAX_MACHINE_MODE >= ((1 << RTX_MACHINE_MODE_BITSIZE) - 1)) fatal ("genopinit range assumptions invalid"); if (!init_rtx_reader_args_cb (argc, argv, handle_arg)) diff --git a/gcc/ira-int.h b/gcc/ira-int.h index e2de47213b4..124e14200b1 100644 --- a/gcc/ira-int.h +++ b/gcc/ira-int.h @@ -280,11 +280,15 @@ struct ira_allocno /* Regno for allocno or cap. */ int regno; /* Mode of the allocno which is the mode of the corresponding - pseudo-register. */ - ENUM_BITFIELD (machine_mode) mode : 8; + pseudo-register. Note the bitsize of mode should be exactly + the same as the definition of rtx_def, aka RTX_MACHINE_MODE_BITSIZE + in rtl.h. */ + ENUM_BITFIELD (machine_mode) mode : 16; /* Widest mode of the allocno which in at least one case could be - for paradoxical subregs where wmode > mode. */ - ENUM_BITFIELD (machine_mode) wmode : 8; + for paradoxical subregs where wmode > mode. Note the bitsize of + wmode should be exactly the same as the definition of rtx_def, + aka RTX_MACHINE_MODE_BITSIZE in rtl.h. */ + ENUM_BITFIELD (machine_mode) wmode : 16; /* Register class which should be used for allocation for given allocno. NO_REGS means that we should use memory. */ ENUM_BITFIELD (reg_class) aclass : 16; diff --git a/gcc/ree.cc b/gcc/ree.cc index 413aec7c8eb..fb011bc907c 100644 --- a/gcc/ree.cc +++ b/gcc/ree.cc @@ -567,7 +567,7 @@ enum ext_modified_kind struct ATTRIBUTE_PACKED ext_modified { /* Mode from which ree has zero or sign extended the destination. */ - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : RTX_MACHINE_MODE_BITSIZE; /* Kind of modification of the insn. */ ENUM_BITFIELD(ext_modified_kind) kind : 2; diff --git a/gcc/rtl-ssa/accesses.h b/gcc/rtl-ssa/accesses.h index c5180b9308a..2e73004cafa 100644 --- a/gcc/rtl-ssa/accesses.h +++ b/gcc/rtl-ssa/accesses.h @@ -253,8 +253,10 @@ private: // Bits for future expansion. unsigned int m_spare : 2; - // The value returned by the accessor above. - machine_mode m_mode : 8; + // The value returned by the accessor above. Note the bitsize of + // m_mode should be exactly the same as the definition of rtx_def, + // aka RTX_MACHINE_MODE_BITSIZE in rtl.h. + machine_mode m_mode : 16; }; // A contiguous array of access_info pointers. Used to represent a diff --git a/gcc/rtl.h b/gcc/rtl.h index f634cab730b..a18ecf7632f 100644 --- a/gcc/rtl.h +++ b/gcc/rtl.h @@ -63,6 +63,9 @@ enum rtx_code { # define NON_GENERATOR_NUM_RTX_CODE ((int) MATCH_OPERAND) #endif +#define RTX_CODE_BITSIZE 8 +#define RTX_MACHINE_MODE_BITSIZE 16 + /* Register Transfer Language EXPRESSIONS CODE CLASSES */ enum rtx_class { @@ -310,10 +313,10 @@ struct GTY((desc("0"), tag("0"), chain_next ("RTX_NEXT (&%h)"), chain_prev ("RTX_PREV (&%h)"))) rtx_def { /* The kind of expression this is. */ - ENUM_BITFIELD(rtx_code) code: 16; + ENUM_BITFIELD(rtx_code) code: RTX_CODE_BITSIZE; /* The kind of value the expression has. */ - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : RTX_MACHINE_MODE_BITSIZE; /* 1 in a MEM if we should keep the alias set for this mem unchanged when we access a component. @@ -2164,7 +2167,7 @@ subreg_shape::operator != (const subreg_shape &other) const inline unsigned HOST_WIDE_INT subreg_shape::unique_id () const { - { STATIC_ASSERT (MAX_MACHINE_MODE <= 256); } + { STATIC_ASSERT (MAX_MACHINE_MODE <= (1 << RTX_MACHINE_MODE_BITSIZE)); } { STATIC_ASSERT (NUM_POLY_INT_COEFFS <= 3); } { STATIC_ASSERT (sizeof (offset.coeffs[0]) <= 2); } int res = (int) inner_mode + ((int) outer_mode << 8); diff --git a/gcc/rtlanal.h b/gcc/rtlanal.h index 5fbed816e20..15aba0dec7a 100644 --- a/gcc/rtlanal.h +++ b/gcc/rtlanal.h @@ -99,8 +99,9 @@ public: unsigned int flags : 16; /* The mode of the reference. If IS_MULTIREG, this is the mode of - REGNO - MULTIREG_OFFSET. */ - machine_mode mode : 8; + REGNO - MULTIREG_OFFSET. Note the bitsize of mode should be exactly + the same as the definition of rtx_def, */ + machine_mode mode : 16; /* If IS_MULTIREG, the offset of REGNO from the start of the register. */ unsigned int multireg_offset : 8; diff --git a/gcc/tree-core.h b/gcc/tree-core.h index a1aea136e75..001d232f433 100644 --- a/gcc/tree-core.h +++ b/gcc/tree-core.h @@ -1680,8 +1680,11 @@ struct GTY(()) tree_type_common { tree attributes; unsigned int uid; + /* Note the bitsize of wmode should be exactly the same as the + definition of rtx_def, aka RTX_MACHINE_MODE_BITSIZE in rtl.h. */ + ENUM_BITFIELD(machine_mode) mode : 16; + unsigned int precision : 16; - ENUM_BITFIELD(machine_mode) mode : 8; unsigned lang_flag_0 : 1; unsigned lang_flag_1 : 1; unsigned lang_flag_2 : 1; @@ -1712,7 +1715,7 @@ struct GTY(()) tree_type_common { unsigned empty_flag : 1; unsigned indivisible_p : 1; unsigned no_named_args_stdarg_p : 1; - unsigned spare : 9; + unsigned spare : 1; alias_set_type alias_set; tree pointer_to; @@ -1770,7 +1773,9 @@ struct GTY(()) tree_decl_common { struct tree_decl_minimal common; tree size; - ENUM_BITFIELD(machine_mode) mode : 8; + /* Note the bitsize of wmode should be exactly the same as the + definition of rtx_def, aka RTX_MACHINE_MODE_BITSIZE in rtl.h. */ + ENUM_BITFIELD(machine_mode) mode : 16; unsigned nonlocal_flag : 1; unsigned virtual_flag : 1;