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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id o11-20020aa7c7cb000000b0050bcbd9b378si591589eds.502.2023.05.08.23.50.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 23:50:24 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=TL4VNHd2; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DEA3638555AA for ; Tue, 9 May 2023 06:49:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DEA3638555AA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683614993; bh=xjA9HSQPS+xnEHU8Gq4AeU+lYXbOUo3pgMnBSm9Z3uI=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=TL4VNHd2gpjVl9JUP7BUmhYF+YYvw1eiioL3BcmGhOtSmWQxsDqXojaJVUcKBrkn5 WnKFs6obTR7qyZ0gOzGMYX16agMaJuQd0+9bqq8CEYRLz8VqYR8jmLRpUlNZMih3rs 3oYPWHn9l0uowQu/3dBEL+BV4lwMSL95xKAH/0FA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id BFDB4385800A for ; Tue, 9 May 2023 06:49:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BFDB4385800A Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CEEAC1063; Mon, 8 May 2023 23:49:52 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E39593F5A1; Mon, 8 May 2023 23:49:07 -0700 (PDT) To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 1/6] aarch64: Fix move-after-intrinsic function-body tests Date: Tue, 9 May 2023 07:48:26 +0100 Message-Id: <20230509064831.1651327-2-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230509064831.1651327-1-richard.sandiford@arm.com> References: <20230509064831.1651327-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-29.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Gcc-patches From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765398307540530603?= X-GMAIL-MSGID: =?utf-8?q?1765398307540530603?= Some of the SVE ACLE asm tests tried to be agnostic about the instruction order, but only one of the alternatives was exercised in practice. This patch fixes latent typos in the other versions. gcc/testsuite/ * gcc.target/aarch64/sve2/acle/asm/aesd_u8.c: Fix expected register allocation in the case where a move occurs after the intrinsic instruction. * gcc.target/aarch64/sve2/acle/asm/aese_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c: Likewise. --- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c | 4 ++-- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c | 4 ++-- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c index 622f5cf4609..384b6ffc9aa 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesd_u8.c @@ -28,13 +28,13 @@ TEST_UNIFORM_Z (aesd_u8_tied2, svuint8_t, ** mov z0\.d, z1\.d ** aesd z0\.b, z0\.b, z2\.b ** | -** aesd z1\.b, z0\.b, z2\.b +** aesd z1\.b, z1\.b, z2\.b ** mov z0\.d, z1\.d ** | ** mov z0\.d, z2\.d ** aesd z0\.b, z0\.b, z1\.b ** | -** aesd z2\.b, z0\.b, z1\.b +** aesd z2\.b, z2\.b, z1\.b ** mov z0\.d, z2\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c index 6555bbb1de7..6381bce1661 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aese_u8.c @@ -28,13 +28,13 @@ TEST_UNIFORM_Z (aese_u8_tied2, svuint8_t, ** mov z0\.d, z1\.d ** aese z0\.b, z0\.b, z2\.b ** | -** aese z1\.b, z0\.b, z2\.b +** aese z1\.b, z1\.b, z2\.b ** mov z0\.d, z1\.d ** | ** mov z0\.d, z2\.d ** aese z0\.b, z0\.b, z1\.b ** | -** aese z2\.b, z0\.b, z1\.b +** aese z2\.b, z2\.b, z1\.b ** mov z0\.d, z2\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c index 4630595ff20..76259326467 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesimc_u8.c @@ -19,7 +19,7 @@ TEST_UNIFORM_Z (aesimc_u8_tied1, svuint8_t, ** mov z0\.d, z1\.d ** aesimc z0\.b, z0\.b ** | -** aesimc z1\.b, z0\.b +** aesimc z1\.b, z1\.b ** mov z0\.d, z1\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c index 6e8acf48f2a..30e83d381dc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/aesmc_u8.c @@ -19,7 +19,7 @@ TEST_UNIFORM_Z (aesmc_u8_tied1, svuint8_t, ** mov z0\.d, z1\.d ** aesmc z0\.b, z0\.b ** | -** aesmc z1\.b, z0\.b +** aesmc z1\.b, z1\.b ** mov z0\.d, z1\.d ** ) ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c index 0ff5746d814..cf6a2a95235 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/sm4e_u32.c @@ -24,7 +24,7 @@ TEST_UNIFORM_Z (sm4e_u32_tied2, svuint32_t, ** mov z0\.d, z1\.d ** sm4e z0\.s, z0\.s, z2\.s ** | -** sm4e z1\.s, z0\.s, z2\.s +** sm4e z1\.s, z1\.s, z2\.s ** mov z0\.d, z1\.d ** ) ** ret