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[8.43.85.97]) by mx.google.com with ESMTPS id kf8-20020a17090776c800b009537e251336si7151ejc.996.2023.05.08.07.13.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:13:47 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=jIeeeFqC; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3151D3856DD2 for ; Mon, 8 May 2023 14:13:30 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-oa1-x2f.google.com (mail-oa1-x2f.google.com [IPv6:2001:4860:4864:20::2f]) by sourceware.org (Postfix) with ESMTPS id 14EFF3858D35 for ; Mon, 8 May 2023 14:13:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 14EFF3858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-195c83a9ed8so2286967fac.0 for ; Mon, 08 May 2023 07:13:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683555183; x=1686147183; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=MfSnKCfVk8s8UF6nJM00wY/eaAJemgpKN4yCW4kzBZI=; b=jIeeeFqCSXKlODRX4cmpJhAvKevs3sY6UHWzKVJ1XWwJUN+dLbJ9KX0tmni8Eu98Dd n/cg+scjwhszAB+/sOCybKvMRps57Tapj93LhdJfV4QMqgoZTJS1ammMgIBUwWZVmiyW BZ7/tbytQh1EBDSYKXyztj3XohPX66EmE2Xq4YIqaq45R1phNXcUS+36UE62w6R/aycY 5jtR4b5xqBiO/5OJ8iuucf8yz3WrZ7JxPGxeTQzRNs8Hvvbzts4dAp5mWtXaLpKCJ744 /YTcoX2KUC0D2KYaC5YfJNwS1FqO3P8OG5kFQnfQ0JUjSuEFvx3sAnlDXUCQrf7AtLU6 8hKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683555183; x=1686147183; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=MfSnKCfVk8s8UF6nJM00wY/eaAJemgpKN4yCW4kzBZI=; b=B4eR/UYNzakfbJlgMr6Hi/D0x2ytQA8Jvvdv78IYqVmoRH6pasagp4cTagAWMvHVDV wa/BaZ68eUnordUSi0VjssJ0oOkCbeEGTs+shZk/fNG27/ju9m5kBQsEXswA4StxW/Tl QaEEtoV67ZR3Pyi6DFysKZXyw9DjnVtyeSx2DFFXwquMfQfwSxSpTqrFf56qVAIJJ/bx QgXC0fHYA0vGfvGqZkihtN0dJ96jj90oms7iKjhqpDXnXN3vubCIKPtLemvQqhnKhXtj DOvm6BjNOsIPwRfdTIzqiY8r334Hy49H/WnOukhnIfWoUijZg9A33QLG3vGh/c0W2ycJ yZng== X-Gm-Message-State: AC+VfDw/Yh5AIHza+LW3/sce110waERKpFOQqpydcg3R2fG8nZ9Uld7X 4EFhOTboaoq6V9aGVOr8Y7knVi6OuXmwiSjCWQc= X-Received: by 2002:a05:6870:8220:b0:17a:ce6b:720 with SMTP id n32-20020a056870822000b0017ace6b0720mr5681076oae.19.1683555183231; Mon, 08 May 2023 07:13:03 -0700 (PDT) Received: from marvin.dc1.ventanamicro.com ([2804:14d:bac2:9b0b::1000]) by smtp.gmail.com with ESMTPSA id du23-20020a0568703a1700b0019280078be5sm4968159oab.6.2023.05.08.07.13.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:13:02 -0700 (PDT) From: Raphael Moreira Zinsly To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, vineetg@rivosinc.com, shihua@iscas.ac.cn, Raphael Moreira Zinsly Subject: [PATCH v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] Date: Mon, 8 May 2023 11:12:56 -0300 Message-Id: <20230508141256.127110-1-rzinsly@ventanamicro.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765335606289003475?= X-GMAIL-MSGID: =?utf-8?q?1765335606289003475?= Changes since v1: - Remove subreg from operand 1. -- >8 -- We were not able to match the CTZ sign extend pattern on RISC-V because it gets optimized to zero extend and/or to ANDI patterns. For the ANDI case, combine scrambles the RTL and generates the extension by using subregs. gcc/ChangeLog: PR target/106888 * config/riscv/bitmanip.md (disi2): Match with any_extend. (disi2_sext): New pattern to match with sign extend using an ANDI instruction. gcc/testsuite/ChangeLog: PR target/106888 * gcc.target/riscv/pr106888.c: New test. * gcc.target/riscv/zbbw.c: Check for ANDI. --- gcc/config/riscv/bitmanip.md | 13 ++++++++++++- gcc/testsuite/gcc.target/riscv/pr106888.c | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/zbbw.c | 1 + 3 files changed, 25 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr106888.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index a27fc3e34a1..064b8f7df8c 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -246,13 +246,24 @@ (define_insn "*disi2" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI + (any_extend:DI (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))] "TARGET_64BIT && TARGET_ZBB" "w\t%0,%1" [(set_attr "type" "") (set_attr "mode" "SI")]) +;; A SImode clz_ctz_pcnt may be extended to DImode via subreg. +(define_insn "*disi2_sext" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (subreg:DI + (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")) 0) + (match_operand:DI 2 "const_int_operand")))] + "TARGET_64BIT && TARGET_ZBB && ((INTVAL (operands[2]) & 0x3f) == 0x3f)" + "w\t%0,%1" + [(set_attr "type" "bitmanip") + (set_attr "mode" "SI")]) + (define_insn "*di2" [(set (match_operand:DI 0 "register_operand" "=r") (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/riscv/pr106888.c b/gcc/testsuite/gcc.target/riscv/pr106888.c new file mode 100644 index 00000000000..77fb8e5b79c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106888.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ + +int +ctz (int i) +{ + int res = __builtin_ctz (i); + return res&0xffff; +} + +/* { dg-final { scan-assembler-times "ctzw" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c index 709743c3b68..f7b2b63853f 100644 --- a/gcc/testsuite/gcc.target/riscv/zbbw.c +++ b/gcc/testsuite/gcc.target/riscv/zbbw.c @@ -23,3 +23,4 @@ popcount (int i) /* { dg-final { scan-assembler-times "clzw" 1 } } */ /* { dg-final { scan-assembler-times "ctzw" 1 } } */ /* { dg-final { scan-assembler-times "cpopw" 1 } } */ +/* { dg-final { scan-assembler-not "andi\t" } } */