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[8.43.85.97]) by mx.google.com with ESMTPS id cf2-20020a170906b2c200b00965a9a34472si1400904ejb.26.2023.05.05.08.00.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 08:00:40 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5D71E385B507 for ; Fri, 5 May 2023 15:00:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id 27A7F3858D20 for ; Fri, 5 May 2023 15:00:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 27A7F3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp64t1683298800tgr10yi5 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 05 May 2023 22:59:58 +0800 (CST) X-QQ-SSF: 01400000000000F0Q000000A0000000 X-QQ-FEAT: k0mQ4ihyJQOx7okF1MED0IGexJx1i82Vz0fXM1mUyfIW/uWKEL/yhYQEEdUUX MM5dyK13qzxx51V50vZSdIx90Wy55TSgLQsH5av9lVdwGL80HdVjY55NVTn6/nf8ke9rxH3 Vo048tB/9CbbgAd7f+I2GjHreHimG7kaBEVuSU6Lwr3QVAuRZ+unsmiD5hzX5JRkceEbcj0 hwJxJcU/TfCQnRCB79FYXN76PtALbWu7/nPtDi4sT9fPAjwjbwrinsaol+eQn+OZ9zi/JJ2 fkWNwgxn9vbzhJNR7LOCZ4Rf+pyRE+TP4ntAlvCq8uKTo7oyoPF1mmNgypQmFvt528a0Und ADnNctC1vWnQQQA0lIhvX0ooli4Ma/cKA673nq+sa1GqLIIy437PN0O40tBiUD2pINjqYeX X-QQ-GoodBg: 2 X-BIZMAIL-ID: 14986371108231285776 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, Juzhe-Zhong Subject: [PATCH V5] RISC-V: Enable basic RVV auto-vectorization support. Date: Fri, 5 May 2023 22:59:56 +0800 Message-Id: <20230505145956.1336111-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765066765443008667?= X-GMAIL-MSGID: =?utf-8?q?1765066765443008667?= From: Juzhe-Zhong Address comments from Robin. gcc/ChangeLog: * config/riscv/riscv-v.cc (preferred_simd_mode): Fix comments. * config/riscv/riscv.cc (riscv_get_arg_info): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Fix function name. * gcc.target/riscv/rvv/autovec/v-1.c: Remove -O3 -ftree-vectorize. * gcc.target/riscv/rvv/autovec/v-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x-2.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Ditto. * gcc.target/riscv/rvv/rvv.exp: Add -O3 -ftree-vectorize. --- gcc/config/riscv/riscv-v.cc | 2 +- gcc/config/riscv/riscv.cc | 9 ++++----- .../gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c | 4 +++- gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c | 7 ++++++- gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 2 +- 31 files changed, 41 insertions(+), 35 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 82510743eb8..1f887f7e747 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -940,7 +940,7 @@ autovec_use_vlmax_p (void) machine_mode preferred_simd_mode (scalar_mode mode) { - /* We only enable auto-vectorization when TARGET_MIN_VLEN < 128 && + /* We will disable auto-vectorization when TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2. Since GCC loop vectorizer report ICE when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*. in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8d3cd4261d2..aa985c2f456 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3791,12 +3791,11 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, info->gpr_offset = cum->num_gprs; info->fpr_offset = cum->num_fprs; - /* TODO: Currently, it will produce ICE for --param + /* TODO: Currently, it will cause an ICE for --param riscv-autovec-preference=fixed-vlmax. So, we just return NULL_RTX here - let GCC genearte loads/stores. Ideally, GCC should either report - Warning message to tell user do not use RVV vector type in function - arg, or GCC just support function arg calling convention for RVV - directly. */ + let GCC generate loads/stores. Ideally, we should either warn the user not + to use an RVV vector type as function argument or support the calling + convention directly. */ if (riscv_v_ext_mode_p (mode)) return NULL_RTX; if (named) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c index d083115aab4..09e8396936e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c @@ -5,7 +5,7 @@ void f (char*); -void stach_check_alloca_1 (vuint8m1_t data, uint8_t *base, int y, ...) +void stack_check_alloca_1 (vuint8m1_t data, uint8_t *base, int y, ...) { vuint8m8_t v0, v8, v16, v24; asm volatile ("nop" @@ -20,3 +20,5 @@ void stach_check_alloca_1 (vuint8m1_t data, uint8_t *base, int y, ...) char* pStr = (char*)__builtin_alloca(y); f(pStr); } + +/* Compiler should not cause an ICE in this testcase. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c index 7ff84f60749..e5e54d08d3e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c @@ -1,4 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" + +/* Currently, we don't support SLP auto-vectorization for VLA. But it's + necessary that we add this testcase here to make sure such unsupported SLP + auto-vectorization will not cause an ICE. We will enable "vect" checking when + we support SLP auto-vectorization for VLA in the future. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c index dc22eefbd36..397d219447b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c index 36f6d98a5cb..066d4ae7f84 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c index 794f28e73bd..9c9123d75f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c index 8e68b9932b4..e0f549aec9e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c index d5e36190b31..ef70c006ec5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c index d154df4c4ba..3c01e4f6c7c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve32f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fno-vect-cost-model -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c index 68e7696ed65..80e69ee8e66 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c index f8860a36332..f7be76965ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c index c26c2c95afb..f1d04b46656 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c index 3a6a3aa1261..48c810a08b0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c index d1aaf3f4297..f025f72c4d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve32x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c index 0d03536389f..24300721f6b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c index ca423285011..283752d479a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c index 40fcbdf1dfb..564cc6fa5c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c index 4c6c7e2fb3b..f87c6283e2e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c index b8253476973..f82610a4bfc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64d_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c index e7900b82215..aac10b6d2ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c index 1c0e8c2785b..781f3bbce73 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c index 0f9ff7a6105..6159e84fc71 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c index daf4a4e8e64..e4c8c056077 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c index 3866e45546c..133380e6844 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64f_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c index 4c190c303c1..bac310af690 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c index 66bb1f44170..5ec8906fd2b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c index e30a6bce18b..fedd9a0228c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c index 6920a395d1c..67be8501f66 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c @@ -1,4 +1,4 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=scalable -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c index d8b60babf9a..1ad74916168 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */ +/* { dg-options "-march=rv32gc_zve64x_zvl128b -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax -fdump-tree-vect-details -save-temps" } */ #include "template-1.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 49bb6012af6..0d5481085e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -47,7 +47,7 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ "" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ - "" $CFLAGS + "-O3 -ftree-vectorize" $CFLAGS set AUTOVEC_TEST_OPTS [list \ {-ftree-vectorize -O3 --param riscv-autovec-lmul=m1} \