| Message ID | 20230505083930.101210-6-christophe.lyon@arm.com |
|---|---|
| State | Accepted |
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To: <gcc-patches@gcc.gnu.org>, <kyrylo.tkachov@arm.com>,
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CC: Christophe Lyon <christophe.lyon@arm.com>
Subject: [PATCH 06/23] arm: [MVE intrinsics] factorize vabdq
Date: Fri, 5 May 2023 10:39:13 +0200
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From: Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org>
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|
| Series |
[01/23] arm: [MVE intrinsics] add binary_round_lshift shape
|
|
Checks
| Context | Check | Description |
|---|---|---|
| snail/gcc-patch-check | success | Github commit url |
Commit Message
Christophe Lyon
May 5, 2023, 8:39 a.m. UTC
2022-09-08 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_FP_M_BINARY): Add vabdq. (MVE_FP_VABDQ_ONLY): New. (mve_insn): Add vabd. * config/arm/mve.md (mve_vabdq_f<mode>): Move into ... (@mve_<mve_insn>q_f<mode>): ... this. (mve_vabdq_m_f<mode>): Remove. --- gcc/config/arm/iterators.md | 9 +++++++-- gcc/config/arm/mve.md | 25 +++++-------------------- 2 files changed, 12 insertions(+), 22 deletions(-)
Comments
> -----Original Message----- > From: Christophe Lyon <christophe.lyon@arm.com> > Sent: Friday, May 5, 2023 9:39 AM > To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; > Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford > <Richard.Sandiford@arm.com> > Cc: Christophe Lyon <Christophe.Lyon@arm.com> > Subject: [PATCH 06/23] arm: [MVE intrinsics] factorize vabdq > > 2022-09-08 Christophe Lyon <christophe.lyon@arm.com> > > gcc/ > * config/arm/iterators.md (MVE_FP_M_BINARY): Add vabdq. > (MVE_FP_VABDQ_ONLY): New. > (mve_insn): Add vabd. > * config/arm/mve.md (mve_vabdq_f<mode>): Move into ... > (@mve_<mve_insn>q_f<mode>): ... this. > (mve_vabdq_m_f<mode>): Remove. Ok. Thanks, Kyrill > --- > gcc/config/arm/iterators.md | 9 +++++++-- > gcc/config/arm/mve.md | 25 +++++-------------------- > 2 files changed, 12 insertions(+), 22 deletions(-) > > diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md > index c53b42a86e9..3133642ea82 100644 > --- a/gcc/config/arm/iterators.md > +++ b/gcc/config/arm/iterators.md > @@ -466,6 +466,7 @@ (define_int_iterator MVE_RSHIFT_N [ > ]) > > (define_int_iterator MVE_FP_M_BINARY [ > + VABDQ_M_F > VADDQ_M_F > VMULQ_M_F > VSUBQ_M_F > @@ -490,6 +491,10 @@ (define_int_iterator MVE_FP_N_BINARY [ > VSUBQ_N_F > ]) > > +(define_int_iterator MVE_FP_VABDQ_ONLY [ > + VABDQ_F > + ]) > + > (define_int_iterator MVE_FP_CREATE_ONLY [ > VCREATEQ_F > ]) > @@ -501,8 +506,8 @@ (define_code_attr mve_addsubmul [ > ]) > > (define_int_attr mve_insn [ > - (VABDQ_M_S "vabd") (VABDQ_M_U "vabd") > - (VABDQ_S "vabd") (VABDQ_U "vabd") > + (VABDQ_M_S "vabd") (VABDQ_M_U "vabd") (VABDQ_M_F > "vabd") > + (VABDQ_S "vabd") (VABDQ_U "vabd") (VABDQ_F "vabd") > (VADDQ_M_N_S "vadd") (VADDQ_M_N_U "vadd") > (VADDQ_M_N_F "vadd") > (VADDQ_M_S "vadd") (VADDQ_M_U "vadd") (VADDQ_M_F > "vadd") > (VADDQ_N_S "vadd") (VADDQ_N_U "vadd") (VADDQ_N_F > "vadd") > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index fb1076aef73..c8cb4e430ac 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -1451,17 +1451,17 @@ (define_insn "mve_vrshrq_n_<supf><mode>" > ]) > > ;; > -;; [vabdq_f]) > +;; [vabdq_f] > ;; > -(define_insn "mve_vabdq_f<mode>" > +(define_insn "@mve_<mve_insn>q_f<mode>" > [ > (set (match_operand:MVE_0 0 "s_register_operand" "=w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" > "w") > (match_operand:MVE_0 2 "s_register_operand" "w")] > - VABDQ_F)) > + MVE_FP_VABDQ_ONLY)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vabd.f%#<V_sz_elem> %q0, %q1, %q2" > + "<mve_insn>.f%#<V_sz_elem>\t%q0, %q1, %q2" > [(set_attr "type" "mve_move") > ]) > > @@ -5483,24 +5483,9 @@ (define_insn "mve_vrmlsldavhaxq_p_sv4si" > "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3" > [(set_attr "type" "mve_move") > (set_attr "length""8")]) > -;; > -;; [vabdq_m_f]) > -;; > -(define_insn "mve_vabdq_m_f<mode>" > - [ > - (set (match_operand:MVE_0 0 "s_register_operand" "=w") > - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > - (match_operand:MVE_0 2 "s_register_operand" "w") > - (match_operand:MVE_0 3 "s_register_operand" "w") > - (match_operand:<MVE_VPRED> 4 > "vpr_register_operand" "Up")] > - VABDQ_M_F)) > - ] > - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vpst\;vabdt.f%#<V_sz_elem> %q0, %q2, %q3" > - [(set_attr "type" "mve_move") > - (set_attr "length""8")]) > > ;; > +;; [vabdq_m_f] > ;; [vaddq_m_f] > ;; [vsubq_m_f] > ;; [vmulq_m_f] > -- > 2.34.1
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index c53b42a86e9..3133642ea82 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -466,6 +466,7 @@ (define_int_iterator MVE_RSHIFT_N [ ]) (define_int_iterator MVE_FP_M_BINARY [ + VABDQ_M_F VADDQ_M_F VMULQ_M_F VSUBQ_M_F @@ -490,6 +491,10 @@ (define_int_iterator MVE_FP_N_BINARY [ VSUBQ_N_F ]) +(define_int_iterator MVE_FP_VABDQ_ONLY [ + VABDQ_F + ]) + (define_int_iterator MVE_FP_CREATE_ONLY [ VCREATEQ_F ]) @@ -501,8 +506,8 @@ (define_code_attr mve_addsubmul [ ]) (define_int_attr mve_insn [ - (VABDQ_M_S "vabd") (VABDQ_M_U "vabd") - (VABDQ_S "vabd") (VABDQ_U "vabd") + (VABDQ_M_S "vabd") (VABDQ_M_U "vabd") (VABDQ_M_F "vabd") + (VABDQ_S "vabd") (VABDQ_U "vabd") (VABDQ_F "vabd") (VADDQ_M_N_S "vadd") (VADDQ_M_N_U "vadd") (VADDQ_M_N_F "vadd") (VADDQ_M_S "vadd") (VADDQ_M_U "vadd") (VADDQ_M_F "vadd") (VADDQ_N_S "vadd") (VADDQ_N_U "vadd") (VADDQ_N_F "vadd") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index fb1076aef73..c8cb4e430ac 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1451,17 +1451,17 @@ (define_insn "mve_vrshrq_n_<supf><mode>" ]) ;; -;; [vabdq_f]) +;; [vabdq_f] ;; -(define_insn "mve_vabdq_f<mode>" +(define_insn "@mve_<mve_insn>q_f<mode>" [ (set (match_operand:MVE_0 0 "s_register_operand" "=w") (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") (match_operand:MVE_0 2 "s_register_operand" "w")] - VABDQ_F)) + MVE_FP_VABDQ_ONLY)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vabd.f%#<V_sz_elem> %q0, %q1, %q2" + "<mve_insn>.f%#<V_sz_elem>\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) @@ -5483,24 +5483,9 @@ (define_insn "mve_vrmlsldavhaxq_p_sv4si" "vpst\;vrmlsldavhaxt.s32\t%Q0, %R0, %q2, %q3" [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vabdq_m_f]) -;; -(define_insn "mve_vabdq_m_f<mode>" - [ - (set (match_operand:MVE_0 0 "s_register_operand" "=w") - (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") - (match_operand:MVE_0 2 "s_register_operand" "w") - (match_operand:MVE_0 3 "s_register_operand" "w") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VABDQ_M_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vabdt.f%#<V_sz_elem> %q0, %q2, %q3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) ;; +;; [vabdq_m_f] ;; [vaddq_m_f] ;; [vsubq_m_f] ;; [vmulq_m_f]