From patchwork Fri May 5 08:39:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 90363 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp247609vqo; Fri, 5 May 2023 01:52:20 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ73FzbhoofyzhIXVwTGoGpgW4nDRXgXvW+8E8WWUnvk4eh97u0JizD+CTcnuUXqAh2Il+iC X-Received: by 2002:a17:907:980a:b0:94a:74b8:7a79 with SMTP id ji10-20020a170907980a00b0094a74b87a79mr536231ejc.59.1683276739949; Fri, 05 May 2023 01:52:19 -0700 (PDT) Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id a12-20020a1709066d4c00b00965ace68e4fsi918985ejt.254.2023.05.05.01.52.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 01:52:19 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=fRJAWDYg; arc=fail (signature failed); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 70EB93829BF4 for ; Fri, 5 May 2023 08:45:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 70EB93829BF4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683276343; bh=hOGDbxSMfAJPvdtsX+ZM67r5R3VWAjYnVFmI9SGcEb0=; h=To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=fRJAWDYgheZsxv1X9gDMGjoHi8af+zXXTK80m8FfKyHtxlawqJNA/SnHUGswxBqPg 0AT7mw/ncJ5kM3lORFcOtckGW1YIGS2KbxlxU5VDA/Ob+ccV7MZR6r+RKm26TqgphL gO6NgeKxOMqG3xpXZ0iPSHUwLyILPSxPbThq6UxA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2063.outbound.protection.outlook.com [40.107.247.63]) by sourceware.org (Postfix) with ESMTPS id 99072385701D for ; Fri, 5 May 2023 08:40:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 99072385701D Received: from AS4P191CA0006.EURP191.PROD.OUTLOOK.COM (2603:10a6:20b:5d5::17) by PAWPR08MB8814.eurprd08.prod.outlook.com (2603:10a6:102:336::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.27; Fri, 5 May 2023 08:40:14 +0000 Received: from AM7EUR03FT025.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:5d5:cafe::b2) by AS4P191CA0006.outlook.office365.com (2603:10a6:20b:5d5::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.27 via Frontend Transport; Fri, 5 May 2023 08:40:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT025.mail.protection.outlook.com (100.127.140.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.27 via Frontend Transport; Fri, 5 May 2023 08:40:14 +0000 Received: ("Tessian outbound 945aec65ec65:v136"); Fri, 05 May 2023 08:40:14 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: cb0d612faeca2bbe X-CR-MTA-TID: 64aa7808 Received: from da2da6cd5362.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 56A55361-4D99-4A0D-9BB6-6E8B18E427F7.1; Fri, 05 May 2023 08:40:02 +0000 Received: from EUR04-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id da2da6cd5362.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 05 May 2023 08:40:02 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hszomLco5NRuFkmKa/91gtqYaEWczIZSF5bk1BuHDElS8D8DUfaT/pGeJFBhYWUW4yxMIVY+ebBobH1DAcrQuGnKsWWbduoG7l0T/7bmux1orkndxQBbkgJ7SwhwRIyQ3cOp3C2EH5sv8Zxx7Bgv3+LUj6mn/n6b83PXqtSNu3KRrSa8bOwlHRp003JjtVsiRu3Lxu7m8Epll96vEtE4f8ioEvG28Bs1KdDw3EubL1Ic0ZL/cfmHSlEMlpouPN4JpfmWjs+BGID9+BstkET67EEPRfbBaBIrYHpzHSw17fej1/C0FaMGefXOGxT9djijjV33vWW7VWSeueJ5ABnMFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hOGDbxSMfAJPvdtsX+ZM67r5R3VWAjYnVFmI9SGcEb0=; b=Tbfulo2WRq2pY8vrzmcMwYbG3mgUhlrl5nHuC2HBAQCbvduZJrIptRdi3/OI1LlLVOLI45IumfUxwIaJ51ZhFhEBJyDsGs1TxDxpLMW7cjxQTO2OPTbj7Z678IwIM9pCPRbmCOs4C49JMgc5U7kBb5RuAiRK3IaaAn3hpooqv9Rs52WtwLY20PgZ4oCjXwz2S+Gbg9OcdPITjv/Rq7/UAXqb6A8dqWjVFWldVMweJObnIBb9rMTWqkv5q4G+jpSMFw2eVBbXlTbJE2eUrchUrC4z4i2Ei6x7hinks52uO8P9C03s7xLmvU36P4ZHwb5Gu1WVn8tjPEhYFZW112qlfg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from AS9PR07CA0006.eurprd07.prod.outlook.com (2603:10a6:20b:46c::7) by PA4PR08MB6237.eurprd08.prod.outlook.com (2603:10a6:102:f3::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.27; Fri, 5 May 2023 08:39:58 +0000 Received: from AM7EUR03FT024.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:46c:cafe::74) by AS9PR07CA0006.outlook.office365.com (2603:10a6:20b:46c::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.12 via Frontend Transport; Fri, 5 May 2023 08:39:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT024.mail.protection.outlook.com (100.127.140.238) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6363.27 via Frontend Transport; Fri, 5 May 2023 08:39:58 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 5 May 2023 08:39:54 +0000 Received: from e129018.arm.com (10.57.22.112) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 5 May 2023 08:39:54 +0000 To: , , , CC: Christophe Lyon Subject: [PATCH 20/23] arm: [MVE intrinsics] rework vqrshrunbq vqrshruntq vqshrunbq vqshruntq Date: Fri, 5 May 2023 10:39:27 +0200 Message-ID: <20230505083930.101210-20-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505083930.101210-1-christophe.lyon@arm.com> References: <20230505083930.101210-1-christophe.lyon@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT024:EE_|PA4PR08MB6237:EE_|AM7EUR03FT025:EE_|PAWPR08MB8814:EE_ X-MS-Office365-Filtering-Correlation-Id: 0bf1dfaf-5cf2-4f6f-dc5d-08db4d44589f x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: q5FiTuhDM6nb1Ri7aTGlo6+Fzg4x6TGNmx2v+8Twj60OUWP8nJSSCx5V8q22gcQz8lA1uWhSVdJAj1UksP3jaukJyyq9JovsuBJF3ivjGo1E5QbezyZWK4Sr22/J/0vhbgWBV4KjTVW9TIe1ZSugHZYmybR1+aGQzvCDGwhLkoEBPnr5Aw2I7Y7HRMX3DBA596lAijt/XdgItWfQHUDrxYDZSs3bz7R2BEC0Qk8Q1reWH7D7iT7Ox1kksGjWwzsdaco4p+AfeeGYmhQc8qJJAyEUq8wZ4mmJSbvKyE+PbBrv9plsUybvZ/JDONblYOJQ5T14h3gOmthpabGIgwFnE2g8eHg2YNl9M+eSyoV64ubkJQ99GyYjyL3AZIVZiAcEnmTj3mpHzTX/cZP3h9u79hFmh9vsCoGssGitLjtTUuiMR8mlcjng2qKrCd8tuAmD9YGf2GRrJMDLHxr3EJzxOA0m4N44dUA8v+FfcUQL3d29C4P0/f+BhX5e3sDWNHieA7rO7DUlEr6WotCWzFCqDmLS9IW+gPhBEoIbJK5ZQcq0xL88I58Q7d+6v5d6G0C+lxYPusIJwFWvIKEbHp4BhRDTO5SKSM3pnXNW8KWP777g8YyPcl5aNqli9zs4ewN+uPR+Ve/SpdN37H45A7I7bbNoGf7t52bhhC7tTjSBnq2W4ynErb+Yxq2BaSWyMKE2CIf+ySxBw8JGDss2w/pB+udxcnn1OpFV+Cucm9/+a2Stzv0YQvFvJMXqtCRFxqFtBmK8R0/VtC+FF2NtEQH4sw== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(136003)(346002)(396003)(39860400002)(376002)(451199021)(46966006)(40470700004)(36840700001)(36756003)(86362001)(110136005)(316002)(6636002)(4326008)(70586007)(70206006)(7696005)(478600001)(6666004)(41300700001)(40480700001)(82310400005)(5660300002)(8676002)(8936002)(2906002)(30864003)(44832011)(34020700004)(356005)(82740400003)(81166007)(186003)(2616005)(36860700001)(26005)(1076003)(426003)(336012)(47076005)(83380400001)(40460700003)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB6237 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT025.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 02b9e2aa-85f8-4c9a-2419-08db4d444f1b X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6MhUJbFZdnOLAvO7qlMxtNPeiu9xtdXdUg42fhuO7Np36vSg/+WWmBMjD0CrK5i5dDRRMRjUw+EQtIG7HDEK+ZvY9Ljz3dwTWD6bv7auTMHrk8rmOXisEhrHur/Wcaco6QLhMznnKa6gAHDI5vBXK/90ABpDMRqiyyIyus4+VCE57P1Uf0Hs/Ud9dK7a2R6qs4f02uZjr9MjZWcxVKaws8kJo1O3m4S7WhAE0q5LdrvZMDq4b+4zs6wpFiNMVRAubaQRShXj/W2Is/SvTPFTCM+F5f96sCPGhXRsDqaLQhKccPFEfYZIwnfcq0KLx/ZRrRtC9+TQpLkRITOIK114bJeAanZafLIdKHhQUaHBmvVMvEGBTcaMheHhJbrizpZ19VKAymxQ84gDTX7wIdV695PEiLEaeqiI9Vq5Td0otidqOpWYj1tEGS/qSHlzxv8ivlGwx77mVg+MxZlUthubJqXQeQC0Mvdr9qERUUb6o2rofrC6yGwTkgMPaWKFtKY5DzBBK+1WAu4L9vHMiJmz2q31SDMHEUoG9yMbZTkiHByvXrXaBHw9kjRg/huiSz44GB4FfSbfx4JICJ07ooPJNoRBnSWFNV3yiF8nsMYhueRJKOk9kqqKmBitdB5IpM7sHS8jiBmnBUBQw7wlq75oQ9+XdPlCYNRrTRt2X1vuc3VGb+qOcIuUoyRkJxdP6iBp9OUg72ZClTxH6RLx/eEqK1xhh/GERqq/HKNWFsJn+3c= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230028)(4636009)(376002)(136003)(39860400002)(346002)(396003)(451199021)(40470700004)(46966006)(36840700001)(40460700003)(7696005)(478600001)(6636002)(4326008)(70206006)(70586007)(316002)(110136005)(36756003)(86362001)(6666004)(47076005)(336012)(426003)(83380400001)(26005)(36860700001)(1076003)(41300700001)(8936002)(5660300002)(8676002)(44832011)(2906002)(30864003)(82310400005)(40480700001)(82740400003)(186003)(81166007)(2616005)(34020700004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2023 08:40:14.2418 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0bf1dfaf-5cf2-4f6f-dc5d-08db4d44589f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT025.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB8814 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765043590584572976?= X-GMAIL-MSGID: =?utf-8?q?1765043590584572976?= Implement vqrshrunbq, vqrshruntq, vqshrunbq, vqshruntq using the new MVE builtins framework. 2022-09-08 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N_NO_U_F): New. (vqshrunbq, vqshruntq, vqrshrunbq, vqrshruntq): New. * config/arm/arm-mve-builtins-base.def (vqshrunbq, vqshruntq) (vqrshrunbq, vqrshruntq): New. * config/arm/arm-mve-builtins-base.h (vqshrunbq, vqshruntq) (vqrshrunbq, vqrshruntq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vqshrunbq, vqshruntq, vqrshrunbq, vqrshruntq. * config/arm/arm_mve.h (vqrshrunbq): Remove. (vqrshruntq): Remove. (vqrshrunbq_m): Remove. (vqrshruntq_m): Remove. (vqrshrunbq_n_s16): Remove. (vqrshrunbq_n_s32): Remove. (vqrshruntq_n_s16): Remove. (vqrshruntq_n_s32): Remove. (vqrshrunbq_m_n_s32): Remove. (vqrshrunbq_m_n_s16): Remove. (vqrshruntq_m_n_s32): Remove. (vqrshruntq_m_n_s16): Remove. (__arm_vqrshrunbq_n_s16): Remove. (__arm_vqrshrunbq_n_s32): Remove. (__arm_vqrshruntq_n_s16): Remove. (__arm_vqrshruntq_n_s32): Remove. (__arm_vqrshrunbq_m_n_s32): Remove. (__arm_vqrshrunbq_m_n_s16): Remove. (__arm_vqrshruntq_m_n_s32): Remove. (__arm_vqrshruntq_m_n_s16): Remove. (__arm_vqrshrunbq): Remove. (__arm_vqrshruntq): Remove. (__arm_vqrshrunbq_m): Remove. (__arm_vqrshruntq_m): Remove. (vqshrunbq): Remove. (vqshruntq): Remove. (vqshrunbq_m): Remove. (vqshruntq_m): Remove. (vqshrunbq_n_s16): Remove. (vqshruntq_n_s16): Remove. (vqshrunbq_n_s32): Remove. (vqshruntq_n_s32): Remove. (vqshrunbq_m_n_s32): Remove. (vqshrunbq_m_n_s16): Remove. (vqshruntq_m_n_s32): Remove. (vqshruntq_m_n_s16): Remove. (__arm_vqshrunbq_n_s16): Remove. (__arm_vqshruntq_n_s16): Remove. (__arm_vqshrunbq_n_s32): Remove. (__arm_vqshruntq_n_s32): Remove. (__arm_vqshrunbq_m_n_s32): Remove. (__arm_vqshrunbq_m_n_s16): Remove. (__arm_vqshruntq_m_n_s32): Remove. (__arm_vqshruntq_m_n_s16): Remove. (__arm_vqshrunbq): Remove. (__arm_vqshruntq): Remove. (__arm_vqshrunbq_m): Remove. (__arm_vqshruntq_m): Remove. --- gcc/config/arm/arm-mve-builtins-base.cc | 13 + gcc/config/arm/arm-mve-builtins-base.def | 4 + gcc/config/arm/arm-mve-builtins-base.h | 4 + gcc/config/arm/arm-mve-builtins.cc | 4 + gcc/config/arm/arm_mve.h | 320 ----------------------- 5 files changed, 25 insertions(+), 320 deletions(-) diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc index c95abe70239..e7d2e0abffc 100644 --- a/gcc/config/arm/arm-mve-builtins-base.cc +++ b/gcc/config/arm/arm-mve-builtins-base.cc @@ -184,6 +184,15 @@ namespace arm_mve { -1, -1, -1, \ UNSPEC##_M_N_S, UNSPEC##_M_N_U, -1)) + /* Helper for builtins with only unspec codes, _m predicated + overrides, only _n version, no unsigned, no floating-point. */ +#define FUNCTION_ONLY_N_NO_U_F(NAME, UNSPEC) FUNCTION \ + (NAME, unspec_mve_function_exact_insn, \ + (-1, -1, -1, \ + UNSPEC##_N_S, -1, -1, \ + -1, -1, -1, \ + UNSPEC##_M_N_S, -1, -1)) + FUNCTION_WITHOUT_N (vabdq, VABDQ) FUNCTION_WITH_RTX_M_N (vaddq, PLUS, VADDQ) FUNCTION_WITH_RTX_M (vandq, AND, VANDQ) @@ -203,8 +212,12 @@ FUNCTION_WITH_M_N_NO_U_F (vqrdmulhq, VQRDMULHQ) FUNCTION_WITH_M_N_R (vqshlq, VQSHLQ) FUNCTION_ONLY_N_NO_F (vqrshrnbq, VQRSHRNBQ) FUNCTION_ONLY_N_NO_F (vqrshrntq, VQRSHRNTQ) +FUNCTION_ONLY_N_NO_U_F (vqrshrunbq, VQRSHRUNBQ) +FUNCTION_ONLY_N_NO_U_F (vqrshruntq, VQRSHRUNTQ) FUNCTION_ONLY_N_NO_F (vqshrnbq, VQSHRNBQ) FUNCTION_ONLY_N_NO_F (vqshrntq, VQSHRNTQ) +FUNCTION_ONLY_N_NO_U_F (vqshrunbq, VQSHRUNBQ) +FUNCTION_ONLY_N_NO_U_F (vqshruntq, VQSHRUNTQ) FUNCTION_WITH_M_N_NO_F (vqsubq, VQSUBQ) FUNCTION (vreinterpretq, vreinterpretq_impl,) FUNCTION_WITHOUT_N_NO_F (vrhaddq, VRHADDQ) diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def index 3dd40086663..50cb2d055e9 100644 --- a/gcc/config/arm/arm-mve-builtins-base.def +++ b/gcc/config/arm/arm-mve-builtins-base.def @@ -36,10 +36,14 @@ DEF_MVE_FUNCTION (vqrdmulhq, binary_opt_n, all_signed, m_or_none) DEF_MVE_FUNCTION (vqrshlq, binary_round_lshift, all_integer, m_or_none) DEF_MVE_FUNCTION (vqrshrnbq, binary_rshift_narrow, integer_16_32, m_or_none) DEF_MVE_FUNCTION (vqrshrntq, binary_rshift_narrow, integer_16_32, m_or_none) +DEF_MVE_FUNCTION (vqrshrunbq, binary_rshift_narrow_unsigned, signed_16_32, m_or_none) +DEF_MVE_FUNCTION (vqrshruntq, binary_rshift_narrow_unsigned, signed_16_32, m_or_none) DEF_MVE_FUNCTION (vqshlq, binary_lshift, all_integer, m_or_none) DEF_MVE_FUNCTION (vqshlq, binary_lshift_r, all_integer, m_or_none) DEF_MVE_FUNCTION (vqshrnbq, binary_rshift_narrow, integer_16_32, m_or_none) DEF_MVE_FUNCTION (vqshrntq, binary_rshift_narrow, integer_16_32, m_or_none) +DEF_MVE_FUNCTION (vqshrunbq, binary_rshift_narrow_unsigned, signed_16_32, m_or_none) +DEF_MVE_FUNCTION (vqshruntq, binary_rshift_narrow_unsigned, signed_16_32, m_or_none) DEF_MVE_FUNCTION (vqsubq, binary_opt_n, all_integer, m_or_none) DEF_MVE_FUNCTION (vreinterpretq, unary_convert, reinterpret_integer, none) DEF_MVE_FUNCTION (vrhaddq, binary, all_integer, mx_or_none) diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h index 9e11ac83681..fcac772bc5b 100644 --- a/gcc/config/arm/arm-mve-builtins-base.h +++ b/gcc/config/arm/arm-mve-builtins-base.h @@ -41,9 +41,13 @@ extern const function_base *const vqrdmulhq; extern const function_base *const vqrshlq; extern const function_base *const vqrshrnbq; extern const function_base *const vqrshrntq; +extern const function_base *const vqrshrunbq; +extern const function_base *const vqrshruntq; extern const function_base *const vqshlq; extern const function_base *const vqshrnbq; extern const function_base *const vqshrntq; +extern const function_base *const vqshrunbq; +extern const function_base *const vqshruntq; extern const function_base *const vqsubq; extern const function_base *const vreinterpretq; extern const function_base *const vrhaddq; diff --git a/gcc/config/arm/arm-mve-builtins.cc b/gcc/config/arm/arm-mve-builtins.cc index 667bbc58483..4fc6160a794 100644 --- a/gcc/config/arm/arm-mve-builtins.cc +++ b/gcc/config/arm/arm-mve-builtins.cc @@ -674,8 +674,12 @@ function_instance::has_inactive_argument () const || (base == functions::vqrshlq && mode_suffix_id == MODE_n) || base == functions::vqrshrnbq || base == functions::vqrshrntq + || base == functions::vqrshrunbq + || base == functions::vqrshruntq || base == functions::vqshrnbq || base == functions::vqshrntq + || base == functions::vqshrunbq + || base == functions::vqshruntq || (base == functions::vrshlq && mode_suffix_id == MODE_n) || base == functions::vrshrnbq || base == functions::vrshrntq diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index ed7852e2460..b2701f1135d 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -113,7 +113,6 @@ #define vrmlaldavhxq(__a, __b) __arm_vrmlaldavhxq(__a, __b) #define vabavq(__a, __b, __c) __arm_vabavq(__a, __b, __c) #define vbicq_m_n(__a, __imm, __p) __arm_vbicq_m_n(__a, __imm, __p) -#define vqrshrunbq(__a, __b, __imm) __arm_vqrshrunbq(__a, __b, __imm) #define vrmlaldavhaq(__a, __b, __c) __arm_vrmlaldavhaq(__a, __b, __c) #define vshlcq(__a, __b, __imm) __arm_vshlcq(__a, __b, __imm) #define vpselq(__a, __b, __p) __arm_vpselq(__a, __b, __p) @@ -190,9 +189,6 @@ #define vqmovnbq_m(__a, __b, __p) __arm_vqmovnbq_m(__a, __b, __p) #define vqmovntq_m(__a, __b, __p) __arm_vqmovntq_m(__a, __b, __p) #define vrev32q_m(__inactive, __a, __p) __arm_vrev32q_m(__inactive, __a, __p) -#define vqrshruntq(__a, __b, __imm) __arm_vqrshruntq(__a, __b, __imm) -#define vqshrunbq(__a, __b, __imm) __arm_vqshrunbq(__a, __b, __imm) -#define vqshruntq(__a, __b, __imm) __arm_vqshruntq(__a, __b, __imm) #define vqmovunbq_m(__a, __b, __p) __arm_vqmovunbq_m(__a, __b, __p) #define vqmovuntq_m(__a, __b, __p) __arm_vqmovuntq_m(__a, __b, __p) #define vsriq_m(__a, __b, __imm, __p) __arm_vsriq_m(__a, __b, __imm, __p) @@ -236,10 +232,6 @@ #define vmulltq_poly_m(__inactive, __a, __b, __p) __arm_vmulltq_poly_m(__inactive, __a, __b, __p) #define vqdmullbq_m(__inactive, __a, __b, __p) __arm_vqdmullbq_m(__inactive, __a, __b, __p) #define vqdmulltq_m(__inactive, __a, __b, __p) __arm_vqdmulltq_m(__inactive, __a, __b, __p) -#define vqrshrunbq_m(__a, __b, __imm, __p) __arm_vqrshrunbq_m(__a, __b, __imm, __p) -#define vqrshruntq_m(__a, __b, __imm, __p) __arm_vqrshruntq_m(__a, __b, __imm, __p) -#define vqshrunbq_m(__a, __b, __imm, __p) __arm_vqshrunbq_m(__a, __b, __imm, __p) -#define vqshruntq_m(__a, __b, __imm, __p) __arm_vqshruntq_m(__a, __b, __imm, __p) #define vrmlaldavhaq_p(__a, __b, __c, __p) __arm_vrmlaldavhaq_p(__a, __b, __c, __p) #define vrmlaldavhaxq_p(__a, __b, __c, __p) __arm_vrmlaldavhaxq_p(__a, __b, __c, __p) #define vrmlsldavhaq_p(__a, __b, __c, __p) __arm_vrmlsldavhaq_p(__a, __b, __c, __p) @@ -889,8 +881,6 @@ #define vcvtq_m_f16_u16(__inactive, __a, __p) __arm_vcvtq_m_f16_u16(__inactive, __a, __p) #define vcvtq_m_f32_s32(__inactive, __a, __p) __arm_vcvtq_m_f32_s32(__inactive, __a, __p) #define vcvtq_m_f32_u32(__inactive, __a, __p) __arm_vcvtq_m_f32_u32(__inactive, __a, __p) -#define vqrshrunbq_n_s16(__a, __b, __imm) __arm_vqrshrunbq_n_s16(__a, __b, __imm) -#define vqrshrunbq_n_s32(__a, __b, __imm) __arm_vqrshrunbq_n_s32(__a, __b, __imm) #define vrmlaldavhaq_s32(__a, __b, __c) __arm_vrmlaldavhaq_s32(__a, __b, __c) #define vrmlaldavhaq_u32(__a, __b, __c) __arm_vrmlaldavhaq_u32(__a, __b, __c) #define vshlcq_s8(__a, __b, __imm) __arm_vshlcq_s8(__a, __b, __imm) @@ -1203,9 +1193,6 @@ #define vcmpneq_m_f16(__a, __b, __p) __arm_vcmpneq_m_f16(__a, __b, __p) #define vcmpneq_m_n_f16(__a, __b, __p) __arm_vcmpneq_m_n_f16(__a, __b, __p) #define vmvnq_m_n_u16(__inactive, __imm, __p) __arm_vmvnq_m_n_u16(__inactive, __imm, __p) -#define vqrshruntq_n_s16(__a, __b, __imm) __arm_vqrshruntq_n_s16(__a, __b, __imm) -#define vqshrunbq_n_s16(__a, __b, __imm) __arm_vqshrunbq_n_s16(__a, __b, __imm) -#define vqshruntq_n_s16(__a, __b, __imm) __arm_vqshruntq_n_s16(__a, __b, __imm) #define vcvtmq_m_u16_f16(__inactive, __a, __p) __arm_vcvtmq_m_u16_f16(__inactive, __a, __p) #define vcvtnq_m_u16_f16(__inactive, __a, __p) __arm_vcvtnq_m_u16_f16(__inactive, __a, __p) #define vcvtpq_m_u16_f16(__inactive, __a, __p) __arm_vcvtpq_m_u16_f16(__inactive, __a, __p) @@ -1278,9 +1265,6 @@ #define vcmpneq_m_f32(__a, __b, __p) __arm_vcmpneq_m_f32(__a, __b, __p) #define vcmpneq_m_n_f32(__a, __b, __p) __arm_vcmpneq_m_n_f32(__a, __b, __p) #define vmvnq_m_n_u32(__inactive, __imm, __p) __arm_vmvnq_m_n_u32(__inactive, __imm, __p) -#define vqrshruntq_n_s32(__a, __b, __imm) __arm_vqrshruntq_n_s32(__a, __b, __imm) -#define vqshrunbq_n_s32(__a, __b, __imm) __arm_vqshrunbq_n_s32(__a, __b, __imm) -#define vqshruntq_n_s32(__a, __b, __imm) __arm_vqshruntq_n_s32(__a, __b, __imm) #define vcvtmq_m_u32_f32(__inactive, __a, __p) __arm_vcvtmq_m_u32_f32(__inactive, __a, __p) #define vcvtnq_m_u32_f32(__inactive, __a, __p) __arm_vcvtnq_m_u32_f32(__inactive, __a, __p) #define vcvtpq_m_u32_f32(__inactive, __a, __p) __arm_vcvtpq_m_u32_f32(__inactive, __a, __p) @@ -1466,14 +1450,6 @@ #define vqdmulltq_m_n_s16(__inactive, __a, __b, __p) __arm_vqdmulltq_m_n_s16(__inactive, __a, __b, __p) #define vqdmulltq_m_s32(__inactive, __a, __b, __p) __arm_vqdmulltq_m_s32(__inactive, __a, __b, __p) #define vqdmulltq_m_s16(__inactive, __a, __b, __p) __arm_vqdmulltq_m_s16(__inactive, __a, __b, __p) -#define vqrshrunbq_m_n_s32(__a, __b, __imm, __p) __arm_vqrshrunbq_m_n_s32(__a, __b, __imm, __p) -#define vqrshrunbq_m_n_s16(__a, __b, __imm, __p) __arm_vqrshrunbq_m_n_s16(__a, __b, __imm, __p) -#define vqrshruntq_m_n_s32(__a, __b, __imm, __p) __arm_vqrshruntq_m_n_s32(__a, __b, __imm, __p) -#define vqrshruntq_m_n_s16(__a, __b, __imm, __p) __arm_vqrshruntq_m_n_s16(__a, __b, __imm, __p) -#define vqshrunbq_m_n_s32(__a, __b, __imm, __p) __arm_vqshrunbq_m_n_s32(__a, __b, __imm, __p) -#define vqshrunbq_m_n_s16(__a, __b, __imm, __p) __arm_vqshrunbq_m_n_s16(__a, __b, __imm, __p) -#define vqshruntq_m_n_s32(__a, __b, __imm, __p) __arm_vqshruntq_m_n_s32(__a, __b, __imm, __p) -#define vqshruntq_m_n_s16(__a, __b, __imm, __p) __arm_vqshruntq_m_n_s16(__a, __b, __imm, __p) #define vrmlaldavhaq_p_s32(__a, __b, __c, __p) __arm_vrmlaldavhaq_p_s32(__a, __b, __c, __p) #define vrmlaldavhaq_p_u32(__a, __b, __c, __p) __arm_vrmlaldavhaq_p_u32(__a, __b, __c, __p) #define vrmlaldavhaxq_p_s32(__a, __b, __c, __p) __arm_vrmlaldavhaxq_p_s32(__a, __b, __c, __p) @@ -4445,20 +4421,6 @@ __arm_vbicq_m_n_u32 (uint32x4_t __a, const int __imm, mve_pred16_t __p) return __builtin_mve_vbicq_m_n_uv4si (__a, __imm, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshrunbq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) -{ - return __builtin_mve_vqrshrunbq_n_sv8hi (__a, __b, __imm); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshrunbq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) -{ - return __builtin_mve_vqrshrunbq_n_sv4si (__a, __b, __imm); -} - __extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrmlaldavhaq_s32 (int64_t __a, int32x4_t __b, int32x4_t __c) @@ -6320,27 +6282,6 @@ __arm_vmvnq_m_n_u16 (uint16x8_t __inactive, const int __imm, mve_pred16_t __p) return __builtin_mve_vmvnq_m_n_uv8hi (__inactive, __imm, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshruntq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) -{ - return __builtin_mve_vqrshruntq_n_sv8hi (__a, __b, __imm); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshrunbq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) -{ - return __builtin_mve_vqshrunbq_n_sv8hi (__a, __b, __imm); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshruntq_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm) -{ - return __builtin_mve_vqshruntq_n_sv8hi (__a, __b, __imm); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vqmovunbq_m_s16 (uint8x16_t __a, int16x8_t __b, mve_pred16_t __p) @@ -6537,27 +6478,6 @@ __arm_vmvnq_m_n_u32 (uint32x4_t __inactive, const int __imm, mve_pred16_t __p) return __builtin_mve_vmvnq_m_n_uv4si (__inactive, __imm, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshruntq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) -{ - return __builtin_mve_vqrshruntq_n_sv4si (__a, __b, __imm); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshrunbq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) -{ - return __builtin_mve_vqshrunbq_n_sv4si (__a, __b, __imm); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshruntq_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm) -{ - return __builtin_mve_vqshruntq_n_sv4si (__a, __b, __imm); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vqmovunbq_m_s32 (uint16x8_t __a, int32x4_t __b, mve_pred16_t __p) @@ -7797,62 +7717,6 @@ __arm_vqdmulltq_m_s16 (int32x4_t __inactive, int16x8_t __a, int16x8_t __b, mve_p return __builtin_mve_vqdmulltq_m_sv8hi (__inactive, __a, __b, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshrunbq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqrshrunbq_m_n_sv4si (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshrunbq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqrshrunbq_m_n_sv8hi (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshruntq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqrshruntq_m_n_sv4si (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshruntq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqrshruntq_m_n_sv8hi (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshrunbq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqshrunbq_m_n_sv4si (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshrunbq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqshrunbq_m_n_sv8hi (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshruntq_m_n_s32 (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqshruntq_m_n_sv4si (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshruntq_m_n_s16 (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vqshruntq_m_n_sv8hi (__a, __b, __imm, __p); -} - __extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrmlaldavhaq_p_s32 (int64_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) @@ -16398,20 +16262,6 @@ __arm_vbicq_m_n (uint32x4_t __a, const int __imm, mve_pred16_t __p) return __arm_vbicq_m_n_u32 (__a, __imm, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshrunbq (uint8x16_t __a, int16x8_t __b, const int __imm) -{ - return __arm_vqrshrunbq_n_s16 (__a, __b, __imm); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshrunbq (uint16x8_t __a, int32x4_t __b, const int __imm) -{ - return __arm_vqrshrunbq_n_s32 (__a, __b, __imm); -} - __extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrmlaldavhaq (int64_t __a, int32x4_t __b, int32x4_t __c) @@ -18260,27 +18110,6 @@ __arm_vmvnq_m (uint16x8_t __inactive, const int __imm, mve_pred16_t __p) return __arm_vmvnq_m_n_u16 (__inactive, __imm, __p); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshruntq (uint8x16_t __a, int16x8_t __b, const int __imm) -{ - return __arm_vqrshruntq_n_s16 (__a, __b, __imm); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshrunbq (uint8x16_t __a, int16x8_t __b, const int __imm) -{ - return __arm_vqshrunbq_n_s16 (__a, __b, __imm); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshruntq (uint8x16_t __a, int16x8_t __b, const int __imm) -{ - return __arm_vqshruntq_n_s16 (__a, __b, __imm); -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vqmovunbq_m (uint8x16_t __a, int16x8_t __b, mve_pred16_t __p) @@ -18477,27 +18306,6 @@ __arm_vmvnq_m (uint32x4_t __inactive, const int __imm, mve_pred16_t __p) return __arm_vmvnq_m_n_u32 (__inactive, __imm, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshruntq (uint16x8_t __a, int32x4_t __b, const int __imm) -{ - return __arm_vqrshruntq_n_s32 (__a, __b, __imm); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshrunbq (uint16x8_t __a, int32x4_t __b, const int __imm) -{ - return __arm_vqshrunbq_n_s32 (__a, __b, __imm); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshruntq (uint16x8_t __a, int32x4_t __b, const int __imm) -{ - return __arm_vqshruntq_n_s32 (__a, __b, __imm); -} - __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vqmovunbq_m (uint16x8_t __a, int32x4_t __b, mve_pred16_t __p) @@ -19737,62 +19545,6 @@ __arm_vqdmulltq_m (int32x4_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred1 return __arm_vqdmulltq_m_s16 (__inactive, __a, __b, __p); } -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshrunbq_m (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vqrshrunbq_m_n_s32 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshrunbq_m (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vqrshrunbq_m_n_s16 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshruntq_m (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vqrshruntq_m_n_s32 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqrshruntq_m (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vqrshruntq_m_n_s16 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshrunbq_m (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vqshrunbq_m_n_s32 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshrunbq_m (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vqshrunbq_m_n_s16 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshruntq_m (uint16x8_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vqshruntq_m_n_s32 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vqshruntq_m (uint8x16_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vqshruntq_m_n_s16 (__a, __b, __imm, __p); -} - __extension__ extern __inline int64_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrmlaldavhaq_p (int64_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) @@ -25799,12 +25551,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) -#define __arm_vqrshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) - #define __arm_vshlcq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlcq_s8 (__ARM_mve_coerce(__p0, int8x16_t), p1, p2), \ @@ -26364,18 +26110,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev16q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev16q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2));}) -#define __arm_vqshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) - -#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) - #define __arm_vqmovnbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -26404,12 +26138,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqmovuntq_m_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqmovuntq_m_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) -#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) - #define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -27544,12 +27272,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) -#define __arm_vqrshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) - #define __arm_vqrdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ @@ -27861,24 +27583,12 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev32q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrev32q_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2));}) -#define __arm_vqshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) - #define __arm_vrev16q_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrev16q_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrev16q_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2));}) -#define __arm_vqrshruntq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) - #define __arm_vqmovuntq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -28718,30 +28428,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint8x16_t]: __arm_vshlltq_m_n_u8 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint16x8_t]: __arm_vshlltq_m_n_u16 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3));}) -#define __arm_vqshruntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshruntq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshruntq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) - -#define __arm_vqshrunbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) - -#define __arm_vqrshrunbq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshrunbq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshrunbq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) - -#define __arm_vqrshruntq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqrshruntq_m_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqrshruntq_m_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) - #define __arm_vmlaldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ @@ -28831,12 +28517,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce1(__p1, int) , p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmvnq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce1(__p1, int) , p2));}) -#define __arm_vqshrunbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int16x8_t]: __arm_vqshrunbq_n_s16 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int32x4_t]: __arm_vqshrunbq_n_s32 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32x4_t), p2));}) - #define __arm_vqshluq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \